公开(公告)号：US20200075582A1

公开(公告)日：2020-03-05

申请号：US16115206

申请日：2018-08-28

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Chao SONG ,  Haitao CHENG

IPC: H01L27/06 ,  H01L27/02 ,  H01L23/522 ,  H01L49/02

Abstract: A resistor-capacitor (RC) delay circuit includes a first capacitor at a first level, a resistor at a second level and a second capacitor at a third level. The second capacitor is electrically connected in parallel with the first capacitor. The second capacitor has a footprint within a footprint of the first capacitor. The resistor is coupled in shunt with the first capacitor and the second capacitor.

公开(公告)号：US20200043863A1

公开(公告)日：2020-02-06

申请号：US16051525

申请日：2018-08-01

Applicant: QUALCOMM Incorporated

Inventor： Haitao CHENG ,  Ye LU ,  Chao SONG

IPC: H01L23/552 ,  H01L23/66

Abstract: Aspects generally relate to tuning a guard ring in an integrated circuit. A guard ring with a gap surrounds a circuit. The level of isolation provided by the guard ring at a particular frequency can be adjusted by coupling a tuning circuit cross the gap of the guard ring. If the circuit in the guard ring is an inductive circuit the level of inductance at a particular frequency can be adjusted by selecting the appropriate tuning circuit across the gap of the guard ring.

公开(公告)号：US20200007105A1

公开(公告)日：2020-01-02

申请号：US16023186

申请日：2018-06-29

Applicant: QUALCOMM Incorporated

Inventor： Chao SONG ,  Haitao CHENG ,  Ye LU ,  Dongjiang QIAO

IPC: H03H7/30 ,  H03H1/02 ,  H03H3/00 ,  H03H7/06 ,  H01L49/02 ,  H01L23/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit (IC) device includes a first resistive strip having an input terminal and an output terminal. The IC device further includes a second resistive strip having a terminal coupled to a voltage. The second resistive strip may be coplanar with the first resistive strip. The IC device further includes a capacitor formed by the first resistive strip and the second resistive strip.

公开(公告)号：US20200051718A1

公开(公告)日：2020-02-13

申请号：US16058928

申请日：2018-08-08

Applicant: QUALCOMM Incorporated

Inventor： Haitao CHENG ,  Chao SONG ,  Ye LU

IPC: H01C3/02 ,  H01L49/02 ,  H01L27/02 ,  G06F17/50 ,  H01C3/16 ,  H01C17/04

Abstract: A co-wound resistor with a low parasitic inductance includes a first resistive strip having an input and a second resistive strip having an output. The second resistive strip has a similar shape as the first resistive strip. The second resistive strip is co-wound in a same direction as the first resistive strip. The second resistive strip and the first resistive strip are configured to generate a mutual inductance that cancels an inductance of the first resistive strip and the second resistive strip. The first interconnect coupling the first resistive strip to the second resistive strip. The first resistive strip, the second resistive strip and the first interconnect are on a same level.

公开(公告)号：US20200044013A1

公开(公告)日：2020-02-06

申请号：US16053124

申请日：2018-08-02

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Haitao CHENG ,  Chao SONG

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/283 ,  H01L21/311

Abstract: A capacitor includes a first conductive element having a plurality of first conductive fingers and a second conductive element having a plurality of second conductive fingers. The first conductive fingers are interdigitated with the second conductive fingers. The capacitor further includes a conformally deposited dielectric material that separates the plurality of first conductive fingers from the plurality of second conductive fingers.

公开(公告)号：US20180315548A1

公开(公告)日：2018-11-01

申请号：US15687234

申请日：2017-08-25

Applicant: QUALCOMM Incorporated

Inventor： Kevin Jia-Nong WANG ,  Chao SONG

IPC: H01G4/012 ,  H01G4/248

CPC classification number: H01G4/012 ,  H01G4/248

Abstract: A capacitor may include a first set of conductive fingers interdigitated with a second set of conductive fingers at an interconnect layer in a preferred direction of the interconnect layer. The capacitor may also include the first set of conductive fingers interdigitated with the second set of conductive fingers at a next interconnect layer in the preferred direction of the next interconnect layer. The capacitor may further include a first set of through finger vias electrically coupling the first set of conductive fingers of the interconnect layer to the first set of conductive fingers of the next interconnect layer.

公开(公告)号：US20220200608A1

公开(公告)日：2022-06-23

申请号：US17125595

申请日：2020-12-17

Applicant: QUALCOMM Incorporated

Inventor： Zhengzheng WU ,  Chao SONG ,  Karthik NAGARAJAN

IPC: H03L7/099 ,  H03L7/093 ,  H03K5/00 ,  H03K3/037 ,  H03K19/20

Abstract: A digital phase-frequency detector characterizes a delay between two input clock signals using a ring oscillator. A cycle count of a ring oscillator signal circulating through a loop in the ring oscillator during the delay provides a coarse measurement of the delay. A phase of the ring oscillator signal in the loop at the end of the delay provides a fine measurement of the delay. A digital phase-locked loop may control an oscillation frequency of a digitally-controlled oscillator responsive to the fine measurement of the delay and control a division within a clock divider responsive to the coarse measurement of the delay.

公开(公告)号：US20220182065A1

公开(公告)日：2022-06-09

申请号：US17449250

申请日：2021-09-28

Applicant: QUALCOMM Incorporated

Inventor： Zhengzheng WU ,  Chao SONG ,  Karthik NAGARAJAN

IPC: H03M1/06 ,  H03M1/82

Abstract: A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

公开(公告)号：US20200083158A1

公开(公告)日：2020-03-12

申请号：US16126406

申请日：2018-09-10

Applicant: QUALCOMM Incorporated

Inventor： Chao SONG ,  Ye LU ,  Haitao CHENG

IPC: H01L23/522 ,  H01L27/01

Abstract: Certain aspects of the present disclosure provide an integrated circuit (IC) that includes at least one of a via-based vertical capacitor structure or a via-based vertical resistor structure. The IC includes a substrate oriented in a horizontal plane, electrically conductive layers disposed above the substrate, and electrically insulative layers disposed above the substrate and interposed between the plurality of electrically conductive layers. At least one of the vertical capacitor structure or the vertical resistor structure is disposed in the electrically conductive layers and the electrically insulative layers.

公开(公告)号：US20190386092A1

公开(公告)日：2019-12-19

申请号：US16009976

申请日：2018-06-15

Applicant: QUALCOMM Incorporated

Inventor： Haitao CHENG ,  Ye LU ,  Chao SONG

IPC: H01L49/02

Abstract: A capacitor has reduced misalignment in the interconnect layers and lower capacitance variance. The capacitor includes a first endcap having a first section and a second section orthogonal to the first section. The capacitor includes a first set of conductive fingers orthogonally coupled to the first section. The capacitor includes a third set of conductive fingers orthogonally coupled to the second section of the endcap and a second endcap parallel to the first section of the endcap. The capacitor includes a second set of conductive fingers orthogonally coupled to a second endcap and interdigitated with the first set of conductive fingers at a first interconnect layer. The capacitor includes a third endcap parallel to the second section of the first endcap and a fourth set of conductive fingers orthogonally coupled to the third endcap and interdigitated with the third set of conductive fingers at the first interconnect layer.