公开(公告)号：US4958225A

公开(公告)日：1990-09-18

申请号：US363554

申请日：1989-06-09

申请人： Qi Bi ,  Gardiner S. Stiles ,  Chien M. Huang

发明人： Qi Bi ,  Gardiner S. Stiles ,  Chien M. Huang

IPC分类号： G06T9/00 ,  H03M7/30

CPC分类号： H04N19/94 ,  G06T9/008 ,  H03M7/3082

摘要： A method for compressing data employing vector quantization is achieved by calculating the norm of an input vector and identifying a reference codebook vector which has a norm which is closest to the norm of the input vector. The distance between the input vector and the reference codebook vector selected is computed and employed to identify a vector space about the reference vector containing a subset of codebook vectors one or more of which may be closer to the input vector than the initially selected reference vector. The closest codebook vector is selected iteratively without the necessity of searching every vector in the codebook.

摘要翻译： 通过计算输入向量的范数并识别具有与输入向量的范数最接近的范数的参考码本向量来实现使用矢量量化来压缩数据的方法。 计算输入向量和所选择的参考码本矢量之间的距离，并用于识别关于包含码本矢量子集的参考矢量的向量空间，其中的一个或多个可能比最初选择的参考矢量更接近于输入向量。 迭代地选择最接近的码本向量，而不需要搜索码本中的每个向量。

公开(公告)号：US07224185B2

公开(公告)日：2007-05-29

申请号：US10523485

申请日：2003-08-05

申请人： John Campbell ,  Gardiner S. Stiles

发明人： John Campbell ,  Gardiner S. Stiles

IPC分类号： H03K19/173 ,  G06F15/16 ,  G06F17/10

CPC分类号： G06F9/3871 ,  G06F9/38 ,  G06F9/3869

摘要： A system of finite state machines built with asynchronous or synchronous logic for controlling the flow of data through computational logic circuits programmed to accomplish a task specified by a user, having one finite state machine associated with each computational logic circuit, having each finite state machine accept data from either one or more predecessor finite state machines or from one or more sources outside the system and furnish data to one or more successor finite state machines or a recipient outside the system, excluding from consideration in determining a clock period for the system logic paths performing the task specified by the user, and providing a means for ensuring that each finite state machine allows sufficient time to elapse for the computational logic circuit associated with that finite state to perform its task.

摘要翻译： 一种用异步或同步逻辑构建的有限状态机系统，用于通过被编程为完成用户指定的任务的计算逻辑电路来控制数据流，该计算逻辑电路具有与每个计算逻辑电路相关联的一个有限状态机，每个有限状态机接受 来自一个或多个前身的有限状态机的数据或来自系统外部的一个或多个源的数据，并将数据提供给一个或多个后继有限状态机或系统外部的接收器，不包括在确定系统逻辑路径的时钟周期时的考虑 执行由用户指定的任务，并提供一种确保每个有限状态机允许足够的时间经过与该有限状态相关联的计算逻辑电路来执行其任务的手段。