公开(公告)号：US20040143724A1

公开(公告)日：2004-07-22

申请号：US10673678

申请日：2003-09-29

Applicant: QuickSilver Technology, Inc.

Inventor： Rojit Jacob ,  Dan MingLun Chuang

IPC: G06F015/00

CPC classification number: G06F15/7867 ,  G06F15/17381

Abstract: The present invention provides an adaptive computing engine (ACE) that includes processing nodes having different capabilities such as arithmetic nodes, bit-manipulation nodes, finite state machine nodes, input/output nodes and a programmable scalar node (PSN). In accordance with one embodiment of the present invention, a common architecture is adaptable to function in either a kernel node, or k-node, or as general purpose RISC node. The k-node acts as a system controller responsible for adapting other nodes to perform selected functions. As a RISC node, the PSN is configured to perform computationally intensive applications such as signal processing.

Abstract translation: 本发明提供一种自适应计算引擎（ACE），其包括具有不同能力的处理节点，例如算术节点，位操作节点，有限状态机节点，输入/输出节点和可编程标量节点（PSN）。 根据本发明的一个实施例，公共架构适用于在内核节点或k节点中或作为通用RISC节点的功能。 k节点充当系统控制器，负责调整其他节点执行选定的功能。 作为RISC节点，PSN被配置为执行诸如信号处理的计算密集型应用。

公开(公告)号：US20040093601A1

公开(公告)日：2004-05-13

申请号：US10289639

申请日：2002-11-07

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  Eugene Hogenauer ,  Bicheng William Wu ,  Dan MingLun Chuang ,  Bjorn Freeman-Benson

IPC: G06F009/00

CPC classification number: G06F17/5022 ,  G06F17/5045

Abstract: A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit. The compiler generates the configuration information, from the scheduled algorithm and the selected adaptive computing circuit version, for the performance of the algorithm by the adaptive computing integrated circuit. In the exemplary embodiments, multiple versions of configuration information may be generated, for different circuit versions, different feature sets, different operating conditions, and different operating modes.

Abstract translation: 提供了一种用于开发自适应计算集成电路和相应配置信息的方法，系统和程序，其中配置信息向自适应计算集成电路提供操作模式。 示例性系统包括调度器，存储器和编译器。 调度器能够利用多个自适应计算描述对象调度所选择的算法，以产生调度算法和所选择的自适应计算电路版本。 存储器用于存储多个自适应计算描述对象和在调度过程期间生成的多个自适应计算电路版本。 所选择的自适应计算电路版本被转换成硬件描述语言，用于制造成自适应计算集成电路。 编译器从调度算法和选择的自适应计算电路版本生成配置信息，以便通过自适应计算集成电路执行算法。 在示例性实施例中，可以针对不同的电路版本，不同的特征集合，不同的操作条件和不同的操作模式来生成配置信息的多个版本。