公开(公告)号：US20030204575A1

公开(公告)日：2003-10-30

申请号：US10135905

申请日：2002-04-29

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  John Watson

IPC: G06F015/177

CPC classification number: G06Q30/06 ,  H04W8/245 ,  Y10S707/99932

Abstract: A system for permitting new, or enhanced, functionality to be transferred to an adaptable device. In a preferred embodiment, the permitted functionality is determined according to an accounting method associated with a user's account. This approach allows a user to contract for specific services, functionality, etc. regardless of changes over time such as changes to data formats, communication protocols, external devices or infrastructure, etc. In a preferred embodiment, the functionality is stored on a ubiquitous communications network such as the Internet. Functionality is transferred to different devices as digital information over the network. This allows hardware functionality to be licensed in many forms. For example, site licenses can be obtained for companies; hardware nulltrialwarenull can be provided to allow limited functionality for a limited time for lower-cost payments, etc.

公开(公告)号：US20040093601A1

公开(公告)日：2004-05-13

申请号：US10289639

申请日：2002-11-07

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  Eugene Hogenauer ,  Bicheng William Wu ,  Dan MingLun Chuang ,  Bjorn Freeman-Benson

IPC: G06F009/00

CPC classification number: G06F17/5022 ,  G06F17/5045

Abstract: A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit. The compiler generates the configuration information, from the scheduled algorithm and the selected adaptive computing circuit version, for the performance of the algorithm by the adaptive computing integrated circuit. In the exemplary embodiments, multiple versions of configuration information may be generated, for different circuit versions, different feature sets, different operating conditions, and different operating modes.

Abstract translation: 提供了一种用于开发自适应计算集成电路和相应配置信息的方法，系统和程序，其中配置信息向自适应计算集成电路提供操作模式。 示例性系统包括调度器，存储器和编译器。 调度器能够利用多个自适应计算描述对象调度所选择的算法，以产生调度算法和所选择的自适应计算电路版本。 存储器用于存储多个自适应计算描述对象和在调度过程期间生成的多个自适应计算电路版本。 所选择的自适应计算电路版本被转换成硬件描述语言，用于制造成自适应计算集成电路。 编译器从调度算法和选择的自适应计算电路版本生成配置信息，以便通过自适应计算集成电路执行算法。 在示例性实施例中，可以针对不同的电路版本，不同的特征集合，不同的操作条件和不同的操作模式来生成配置信息的多个版本。

公开(公告)号：US20040028082A1

公开(公告)日：2004-02-12

申请号：US10013825

申请日：2001-12-10

Applicant: Quicksilver Technology, Inc.

Inventor： Paul L. Master ,  John Watson

IPC: H04J001/02

CPC classification number: G06Q30/02

Abstract: A system for efficient sale of devices that comply with licensed standards. A preferred embodiment of the invention uses a generic, or highly adaptable, hardware device. The device can be adapted to adhere to a specific standard, e.g., code-division multiple access, time-division multiple access, etc., after manufacture such as at the point-of-sale to an end user, prior to distribution, or at some other point in a distribution and sales network. This allows manufacturers, retailers and end users to benefit from more competitive selection of standardized communication, data and other formats. Reduction of manufacturing costs and elimination of shipping, or other transfer and storage costs, is also realized.

Abstract translation: 一种高效销售符合许可标准的设备的系统。 本发明的优选实施例使用通用或高适应性的硬件设备。 该设备可以在分发之前适应于遵守特定标准，例如在诸如销售点的制造之后的码分多址，时分多路访问等到最终用户，或者 在分销和销售网络的其他一点。 这允许制造商，零售商和最终用户从更具竞争力的标准化通信，数据和其他格式的选择中受益。 降低制造成本和消除运输，或其他转运和储存成本也得以实现。

公开(公告)号：US20030115553A1

公开(公告)日：2003-06-19

申请号：US10022776

申请日：2001-12-13

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  W. James Scheuermann

IPC: G06F017/50

CPC classification number: G06F9/30189 ,  G06F9/223 ,  G06F9/30145 ,  G06F9/325

Abstract: A microprocessor architecture including a finite state machine in combination with a microcode instruction cache for executing microinstructions. Microinstructions which would normally result in small sequences of high-repetition looped operations are implemented in a finite state machine (FSM). The use of the FSM is more energy-efficient than looping instructions in a cache or register set. In addition, the flexibility of a cache, or other memory oriented approach, in executing microcode instructions is still available. A microinstruction is identified as an FSM operation (as opposed to a cache operation) by an ID tag. Other fields of the microinstruction can be used to identify the type of FSM circuitry to use, direct configuration of a FSM to implement the microinstruction, indicate that certain fields are to be implemented in one or more FSMs and/or in memory-oriented operations such as in a cache or register.

Abstract translation: 一种微处理器架构，包括与用于执行微指令的微代码指令高速缓存组合的有限状态机。 通常会导致高重复循环操作的小序列的微指令在有限状态机（FSM）中实现。 使用FSM比缓存或寄存器集中的循环指令更节能。 此外，在执行微代码指令时，缓存或其他面向内存的方法的灵活性仍然可用。 通过ID标签将微指令识别为FSM操作（与高速缓存操作相反）。 微指令的其他领域可用于识别要使用的FSM电路的类型，直接配置FSM以实现微指令，指示某些字段将在一个或多个FSM和/或面向内存的操作中实现，例如 如缓存或注册。

公开(公告)号：US20030054774A1

公开(公告)日：2003-03-20

申请号：US10015544

申请日：2001-12-12

Applicant: Quicksilver Technology, Inc.

Inventor： Robert T. Plunkett ,  Ghobad Heidari ,  Paul L. Master

IPC: H04B001/40

CPC classification number: H04L29/06 ,  G06F15/7867 ,  H04L69/329 ,  H04W52/0209 ,  H04W88/02 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D70/142 ,  Y02D70/144

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The exemplary IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. In an exemplary embodiment, some or all of the computational elements are alternately configured to implement two or more functions including a system acquisition function.

Abstract translation: 本发明涉及一种新类型的集成电路和用于自适应或可重新配置计算的新方法。 示例性IC实施例包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络可实时操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，存储器 操作和位级操作。 选择各种固定架构以相对最小化功率消耗并增加自适应计算集成电路的性能，特别适用于移动，手持或其他电池供电的计算应用。 在示例性实施例中，部分或全部计算元件被交替地配置为实现包括系统获取功能的两个或多个功能。

公开(公告)号：US20030140123A1

公开(公告)日：2003-07-24

申请号：US10040100

申请日：2002-01-04

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  Bohumir Uvacek

IPC: G06F015/177

CPC classification number: H04W88/06 ,  H04W48/12

Abstract: The present invention provides a method and apparatus for configuration of adaptive integrated circuitry, to provide one or more operating modes or other functionality in a communication device, such as a cellular telephone, a GSM telephone, another type of mobile telephone or mobile station, or any other type of media communication device, including video, voice or radio, or other forms of multimedia. The adaptive integrated circuitry is configured and reconfigured for multiple tasks, such as channel acquisition, voice transmission, or multimedia and other data processing. In the preferred embodiment, the configuration and reconfiguration occurs to adaptively optimize the performance of the particular activity over time, such as to increase the speed of channel acquisition, increase throughput rates, increase perceived voice and media quality, and decrease the rate of dropped communication sessions.

Abstract translation: 本发明提供了一种用于配置自适应集成电路的方法和装置，以在诸如蜂窝电话，GSM电话，另一类型的移动电话或移动台之类的通信设备中提供一个或多个操作模式或其它功能，或 任何其他类型的媒体通信设备，包括视频，语音或无线电，或其他形式的多媒体。 自适应集成电路被配置和重新配置用于多个任务，例如信道获取，语音传输或多媒体和其他数据处理。 在优选实施例中，发生配置和重新配置以随时间自适应地优化特定活动的性能，例如增加频道获取的速度，增加吞吐率，增加感知语音和媒体质量，以及降低丢弃通信的速率 会话

公开(公告)号：US20030105949A1

公开(公告)日：2003-06-05

申请号：US09997987

申请日：2001-11-30

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  Stephen J. Smith ,  John Watson

IPC: H03K019/177 ,  H01L025/00 ,  G06F001/24 ,  G06F009/00

CPC classification number: G06F15/80 ,  G06F7/57 ,  G06F9/44505 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

Abstract: The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit to provide an operating mode. The preferred executable information modules include configuration information interleaved with operand data, and may also include routing and power control information. The preferred ACE IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract translation: 本发明涉及用于自适应或可重新配置计算的新类别的集成电路的配置。 各种实施例提供用于自适应计算引擎（ACE）集成电路的可执行信息模块以提供操作模式。 优选的可执行信息模块包括与操作数数据交错的配置信息，并且还可以包括路由和功率控制信息。 优选的ACE IC包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络可实时操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，存储器 操作和位级操作。

公开(公告)号：US20020138716A1

公开(公告)日：2002-09-26

申请号：US09815122

申请日：2001-03-22

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  Eugene Hogenauer ,  Walter James Scheuermann

IPC: G06F009/00

CPC classification number: G06F15/7867 ,  G06F13/4027 ,  Y02D10/12 ,  Y02D10/13

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Abstract translation: 本发明涉及一种新类型的集成电路和用于自适应或可重新配置计算的新方法。 优选的IC实施例包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络可实时操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，存储器 操作和位级操作。 选择各种固定架构以相对最小化功率消耗并增加自适应计算集成电路的性能，特别适用于移动，手持或其他电池供电的计算应用。

公开(公告)号：US20040268096A1

公开(公告)日：2004-12-30

申请号：US10606031

申请日：2003-06-25

Applicant: QuickSilver Technology, Inc.

Inventor： Paul L. Master ,  John Watson

IPC: G06F007/38 ,  G06F009/00 ,  G06F009/44 ,  G06F015/00 ,  H04N005/228

CPC classification number: G06F7/5443 ,  G06F7/4806 ,  G06F9/3001 ,  G06F9/3885 ,  G06F9/3897 ,  H03H17/0294

Abstract: The present invention provides a digital imaging apparatus having an optical sensor, an analog-to-digital converter, a plurality of computational elements, and an interconnection network. The optical sensor converts an object image into a detected image, which is then converted to digital image information by the analog-to-digital converter. The plurality of computational elements includes a first computational element having a first fixed architecture and a second computational element having a second, different fixed architecture. The interconnection network is capable of providing a processed digital image from the digital image information by configuring and reconfiguring the plurality of computational elements for performance of a plurality of different imaging functions. The invention may be embodied, for example, as a digital camera, a scanner, a printer, or a dry copier.

Abstract translation: 本发明提供一种具有光学传感器，模数转换器，多个计算元件和互连网络的数字成像设备。 光学传感器将对象图像转换为检测图像，然后通过模数转换器将其转换为数字图像信息。 多个计算元件包括具有第一固定架构的第一计算元件和具有第二不同固定架构的第二计算元件。 互连网络能够通过配置和重新配置用于执行多个不同成像功能的多个计算元件从数字图像信息提供经处理的数字图像。 本发明可以被实现为例如数字照相机，扫描仪，打印机或干式复印机。

公开(公告)号：US20040181614A1

公开(公告)日：2004-09-16

申请号：US10719409

申请日：2003-11-22

Applicant: Quicksilver Technology, Inc.

Inventor： Frederick Curtis Furtek ,  Paul L. Master ,  Robert Thomas Plunkett

IPC: G06F003/00

CPC classification number: G06F13/385 ,  G06F2213/0038

Abstract: A reconfigurable input/output controller (IOC) allows an adaptive computing engine (ACE) to communicate with external devices. The external devices can comprise a separate system on chip (SOC) or can be other devices or resources such as audio/visual output devices, memory, network or other communications, etc. The IOC allows different modes of transfer and performs necessary translation of input and output commands. In one embodiment, the IOC adheres to standard messaging and communication protocol used by other nodes in the ACE. This approach allows a uniform approach to the ACE design and provides advantages in scalability and adaptability of the ACE system. One feature of the invention provides a physical link adapter for accommodating different external communication types such as, RS231, optical, Firewire, universal synchronous bus (USB), etc. The physical link adapter uses a reconfigurable finite state machine, selectable couplings and a bus switch to allow connection of different communication types' signals to a common ACE component such as to an IOC.

Abstract translation: 可重配置输入/输出控制器（IOC）允许自适应计算引擎（ACE）与外部设备进行通信。 外部设备可以包括单独的片上系统（SOC）或者可以是诸如音频/视频输出设备，存储器，网络或其他通信之类的其他设备或资源.IOC允许不同的传输模式并执行输入的必要的转换 并输出命令。 在一个实施例中，IOC遵守ACE中其他节点使用的标准消息和通信协议。 这种方法允许对ACE设计采用统一的方法，并在ACE系统的可扩展性和适应性方面提供优势。 本发明的一个特征提供一种用于适应不同外部通信类型（例如RS231，光学，火线，通用同步总线（USB）等）的物理链路适配器。物理链路适配器使用可重构的有限状态机，可选择的耦合和总线 切换以允许将不同通信类型的信号连接到公共ACE组件，例如IOC。