公开(公告)号：US3839907A

公开(公告)日：1974-10-08

申请号：US34667173

申请日：1973-03-30

Applicant: RCA CORP

Inventor： HANSON R ,  FINEMAN H

IPC: G01L5/00 ,  F02D41/14 ,  G01M15/04 ,  G01M15/00

CPC classification number: G01M15/044

Abstract: A simulated load is applied to an internal combustion engine while testing apparatus analyzes the overall performance of the engine. The simulated load is effected by periodically interrupting the engine ignition to reduce the total developed power of the engine to a value equal to its frictional horse power at the resulting engine speed. The firing ratio of the interruption cycle is preset to a fixed value to allow engine operation under full throttle conditions within acceptable engine speed limits. The difference between the resulting speed and a predetermined test speed provides a criterion for the overall performance evaluation of the internal combustion engine.

Abstract translation: 在测试装置分析发动机的整体性能时，将模拟负载应用于内燃机。 模拟负载通过周期性地中断发动机点火来实现，以将发动机的总开发功率降低到在所得到的发动机转速下等于其摩擦马力的值。 中断循环的点火比例预设为固定值，以允许发动机在全油门条件下在可接受的发动机转速限制内运行。 所得到的速度与预定的测试速度之间的差异为内燃机的整体性能评估提供了标准。

公开(公告)号：US3794854A

公开(公告)日：1974-02-26

申请号：US3794854D

申请日：1972-11-30

Applicant: RCA CORP

Inventor： HANSON R ,  FINEMAN H

IPC: G01R29/027 ,  H03K5/00

CPC classification number: G01R29/0273

Abstract: Circuit for distinguishing signals of relatively long duration (information) on a plurality of input lines from one or more signals of relatively short duration (noise) on these same lines. Any signal present on a line enables a gate for that line which is normally maintained in a primed state by a storage element connected to that line. The enabled gate causes a circuit which is common to all lines to produce a delayed pulse. If, when the delayed pulse occurs, a normally primed gate for a line is still enabled, the storage element of that line is set and the latter disables that gate. If, on the other hand, the normally primed gate is not enabled when the delayed pulse occurs, the storage element is not disturbed and the gate is retained in its primed condition.

Abstract translation: 用于从这些相同线路上的相对较短持续时间（噪声）的一个或多个信号区分多个输入线上的相对较长持续时间（信息）的信号的电路。 存在于线路上的任何信号使得能够通过连接到该线路的存储元件通常保持在初始化状态的线路的门。 使能的栅极导致所有线路共有的电路产生延迟的脉冲。 如果发生延迟脉冲，则仍然启用一条正常引脚的栅极，该行的存储元件被置位，后者禁止该栅极。 另一方面，如果延迟脉冲发生时，正常启动的门不被使能，则存储元件不受干扰，并且门被保持在其初始化状态。