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公开(公告)号：US20220147676A1
公开(公告)日：2022-05-12
申请号：US17517322
申请日：2021-11-02
发明人： Hsing-Han Tseng , Yung-Jen Chen , Yu-Lan Lo
IPC分类号： G06F30/3312 , G06F30/327 , G06F30/323
摘要： An integrated circuit simulation method is performed by a processor and includes: obtaining a register transfer level (RTL) waveform set obtained by performing an RTL simulation based on a circuit, where the circuit is generated in an RTL design stage and includes a register having an internal net and a data output port, and the RTL waveform set includes a first waveform corresponding to the data output port of the register; obtaining a netlist and delay information obtained by performing a logic synthesis based on the circuit, where the netlist includes a first node and a second node, the first node corresponds to the internal net of the register, and the second node corresponds to the data output port of the register; applying the first waveform to the first node; and triggering the register according to the delay information to obtain a second waveform at the second node.
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公开(公告)号：US12039240B2
公开(公告)日：2024-07-16
申请号：US17517322
申请日：2021-11-02
发明人： Hsing-Han Tseng , Yung-Jen Chen , Yu-Lan Lo
IPC分类号： G06F30/3312 , G06F30/323 , G06F30/327 , G06F119/12
CPC分类号： G06F30/3312 , G06F30/323 , G06F30/327 , G06F2119/12
摘要： An integrated circuit simulation method is performed by a processor and includes: obtaining a register transfer level (RTL) waveform set obtained by performing an RTL simulation based on a circuit, where the circuit is generated in an RTL design stage and includes a register having an internal net and a data output port, and the RTL waveform set includes a first waveform corresponding to the data output port of the register; obtaining a netlist and delay information obtained by performing a logic synthesis based on the circuit, where the netlist includes a first node and a second node, the first node corresponds to the internal net of the register, and the second node corresponds to the data output port of the register; applying the first waveform to the first node; and triggering the register according to the delay information to obtain a second waveform at the second node.
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