公开(公告)号：US11227854B2

公开(公告)日：2022-01-18

申请号：US15930418

申请日：2020-05-12

Applicant: Realtek Semiconductor Corp.

Inventor： Chin-Yuan Lo ,  Nan-Chin Chuang ,  Chih-Hao Chang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a carrier substrate including opposite first surface and second surface; a first chip and a second chip mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the first chip has a plurality of high-speed signal pads disposed along its first side adjacent to the second chip, and the second chip has a plurality of data (DQ) pads along its second side adjacent to the first chip; and a plurality of first bonding wires, directly connecting the plurality of high-speed signal pads to the plurality of data (DQ) pads.

公开(公告)号：US20210118846A1

公开(公告)日：2021-04-22

申请号：US15930418

申请日：2020-05-12

Applicant: Realtek Semiconductor Corp.

Inventor： Chin-Yuan Lo ,  Nan-Chin Chuang ,  Chih-Hao Chang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: A semiconductor package includes a carrier substrate including opposite first surface and second surface; a first chip and a second chip mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the first chip has a plurality of high-speed signal pads disposed along its first side adjacent to the second chip, and the second chip has a plurality of data (DQ) pads along its second side adjacent to the first chip; and a plurality of first bonding wires, directly connecting the plurality of high-speed signal pads to the plurality of data (DQ) pads.

公开(公告)号：US12046543B2

公开(公告)日：2024-07-23

申请号：US17679862

申请日：2022-02-24

Applicant: REALTEK SEMICONDUCTOR CORP.

Inventor： Han-Chieh Hsieh ,  Chao-Min Lai ,  Cheng-Chen Huang ,  Nan-Chin Chuang

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: A package substrate and a chip package structure using the same are provided. The package substrate includes a laminated board including first to third wiring layers, a pad array, a plurality of ground conductive structures, and a plurality of power conductive structures. At least one of the ground (or power) conductive structures includes two first ground (or power) conductive posts and a second ground (or power) conductive post. The two first ground (or power) conductive posts and the second ground (or power) conductive post are arranged along a first direction, and the second ground (or power) conductive post is located between two orthographic projections of the two first ground (or power) conductive posts. Each of the ground conductive structures in a first column and each of the power conductive structures in a second column are offset from each other in a second direction.

公开(公告)号：US11553585B2

公开(公告)日：2023-01-10

申请号：US17563326

申请日：2021-12-28

Applicant: REALTEK SEMICONDUCTOR CORP.

Inventor： Chin-Yuan Lo ,  Nan-Chin Chuang ,  Hsin-Hui Lo

IPC: H05K1/02

Abstract: A circuit board and an electronic apparatus using the same are provided. The circuit board includes an integrated-circuit (IC) device arrangement region and an electronic device arrangement region. The circuit board includes a first external wiring layer and an inner wiring layer. The first external wiring layer includes a plurality of first signal traces and a ground extending portion that extend from the IC device arrangement region to the electronic device arrangement region. The inner wiring layer includes a ground portion and an inner signal trace. The ground portion defines an opening region, and the inner signal trace is located in the opening region and extends from a position under the IC device arrangement region to another position under the electronic device region. The ground extending portion and the opening region overlap with each other in a thickness direction of the circuit board.