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    Electronic package structure with a core ground wire and chip thereof
    1.
    发明授权
    Electronic package structure with a core ground wire and chip thereof 有权

    公开(公告)号：US11264352B2

    公开(公告)日：2022-03-01

    申请号：US16897424

    申请日：2020-06-10

    Applicant: REALTEK SEMICONDUCTOR CORP.

    Inventor： Ting-Ying Wu ,  Chien-Hsiang Huang ,  Chin-Yuan Lo ,  Chih-Wei Chang

    IPC: H01L23/00

    Abstract: An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.

    Semiconductor package
    2.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11322474B2

    公开(公告)日：2022-05-03

    申请号：US17192909

    申请日：2021-03-05

    Applicant: Realtek Semiconductor Corp.

    Inventor： Chin-Yuan Lo ,  Chih-Hao Chang ,  Tze-Min Shen

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

    Abstract: A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.

    SEMICONDUCTOR PACKAGE
    3.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210118846A1

    公开(公告)日：2021-04-22

    申请号：US15930418

    申请日：2020-05-12

    Applicant: Realtek Semiconductor Corp.

    Inventor： Chin-Yuan Lo ,  Nan-Chin Chuang ,  Chih-Hao Chang

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

    Abstract: A semiconductor package includes a carrier substrate including opposite first surface and second surface; a first chip and a second chip mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the first chip has a plurality of high-speed signal pads disposed along its first side adjacent to the second chip, and the second chip has a plurality of data (DQ) pads along its second side adjacent to the first chip; and a plurality of first bonding wires, directly connecting the plurality of high-speed signal pads to the plurality of data (DQ) pads.

    Circuit board and electronic apparatus using the same
    4.
    发明授权
    Circuit board and electronic apparatus using the same 有权

    公开(公告)号：US11553585B2

    公开(公告)日：2023-01-10

    申请号：US17563326

    申请日：2021-12-28

    Applicant: REALTEK SEMICONDUCTOR CORP.

    Inventor： Chin-Yuan Lo ,  Nan-Chin Chuang ,  Hsin-Hui Lo

    IPC: H05K1/02

    Abstract: A circuit board and an electronic apparatus using the same are provided. The circuit board includes an integrated-circuit (IC) device arrangement region and an electronic device arrangement region. The circuit board includes a first external wiring layer and an inner wiring layer. The first external wiring layer includes a plurality of first signal traces and a ground extending portion that extend from the IC device arrangement region to the electronic device arrangement region. The inner wiring layer includes a ground portion and an inner signal trace. The ground portion defines an opening region, and the inner signal trace is located in the opening region and extends from a position under the IC device arrangement region to another position under the electronic device region. The ground extending portion and the opening region overlap with each other in a thickness direction of the circuit board.

    Semiconductor package
    5.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11227854B2

    公开(公告)日：2022-01-18

    申请号：US15930418

    申请日：2020-05-12

    Applicant: Realtek Semiconductor Corp.

    Inventor： Chin-Yuan Lo ,  Nan-Chin Chuang ,  Chih-Hao Chang

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

    Abstract: A semiconductor package includes a carrier substrate including opposite first surface and second surface; a first chip and a second chip mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the first chip has a plurality of high-speed signal pads disposed along its first side adjacent to the second chip, and the second chip has a plurality of data (DQ) pads along its second side adjacent to the first chip; and a plurality of first bonding wires, directly connecting the plurality of high-speed signal pads to the plurality of data (DQ) pads.

    SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210327844A1

    公开(公告)日：2021-10-21

    申请号：US17192909

    申请日：2021-03-05

    Applicant: Realtek Semiconductor Corp.

    Inventor： Chin-Yuan Lo ,  Chih-Hao Chang ,  Tze-Min Shen

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

    Abstract: A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.

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