公开(公告)号：US20230396552A1

公开(公告)日：2023-12-07

申请号：US18196620

申请日：2023-05-12

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： CHI-SHAO LAI ,  HSU-TUNG SHIH

IPC分类号： H04L47/24 ,  H04L47/56 ,  H04L41/16

CPC分类号： H04L47/24 ,  H04L47/56 ,  H04L41/16

摘要： A memory control system includes a front-end circuitry, a back-end circuitry, and a traffic scheduling circuitry. The front-end circuitry is configured to receive a plurality of access requests from a plurality of devices, and adjust an order of the plurality of devices to access a memory according to a plurality of control signals. The traffic scheduling circuitry is configured to generate a plurality of traffic data based on the plurality of access requests and analyze the plurality of traffic data based on a neural network model and a predetermined rule, in order to determine the plurality of control signals. The back-end circuitry is configured to adjust a task schedule of the memory according to the plurality of control signals.