公开(公告)号：US11955976B2

公开(公告)日：2024-04-09

申请号：US17973706

申请日：2022-10-26

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Yao-Chia Liu ,  Yuan-Sheng Lee

IPC: H03K5/00 ,  H03K5/131 ,  H03K5/135 ,  H03K5/15 ,  H03K19/173

CPC classification number: H03K5/135 ,  H03K5/131 ,  H03K5/15093 ,  H03K19/1737

Abstract: A quadrant alternate switching phase interpolator includes first and second multiplexer circuits, a phase interpolator circuitry, and a controller circuitry. The first multiplexer circuit outputs one of first and second clock signals to be a first signal in response to first and third bits in a quadrant control code. The second multiplexer circuit outputs one of third and fourth clock signals to be a second signal in response to second and fourth bits in the quadrant control code, and the first, the third, the second, and fourth clock signals are sequentially different in phase by 90 degrees. The phase interpolator circuitry generates an output clock signal in response to the first and the second signals and phase control bits. The controller circuitry performs a bit-shift operation on the phase control bits to adjust a phase of the output clock signal.

公开(公告)号：US11722127B2

公开(公告)日：2023-08-08

申请号：US17880828

申请日：2022-08-04

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Yuan-Sheng Lee ,  Yao-Chia Liu

IPC: H03K5/135 ,  H03K5/00

CPC classification number: H03K5/135 ,  H03K2005/00052

Abstract: A phase interpolator includes phase interpolator circuitries. The phase interpolator circuitries generate an output clock signal from an output node according to phase control bits and clock signals. Phases of the clock signals are different from each other. Each phase circuitry includes phase buffer circuits. Each phase buffer circuit is turned on according a first bit and a second bit of the phase control bits, in order to generate a signal component in the output clock signal according to a corresponding clock signal of the clock signals. Each phase buffer circuit includes a first resistor and a second resistor, and transmits one of a first voltage and a second voltage to the output node according to the corresponding clock signal, in which the first voltage is transmitted to the output node via the first resistor, and the second voltage is transmitted to the output node via the second resistor.