公开(公告)号：US20180039858A1

公开(公告)日：2018-02-08

申请号：US15600741

申请日：2017-05-21

Applicant: Renesas Electronics Corporation

Inventor： Akira UTAGAWA ,  Takaaki SATO ,  Atsushi NAKAMURA ,  Manabu KOIKE ,  Masaya ITOH

IPC: G06K9/62 ,  G06F17/30 ,  G06K9/46

CPC classification number: G06K9/6212 ,  G06F16/5838 ,  G06K9/00791 ,  G06K9/4609 ,  G06K9/4642 ,  G06K9/4652 ,  G06K9/6255 ,  G06K9/68 ,  G06K2009/4666 ,  G06K2009/485

Abstract: An image recognition apparatus 100 includes a gradient feature computation unit 120 configured to calculate, from an image divided into a plurality of blocks, gradient feature values for each of the plurality of blocks, a combination pattern storage unit 160 configured to store a plurality of combination patterns of the gradient feature values, and a co-occurrence feature computation unit 131 configured to calculate a co-occurrence feature value in a plurality of blocks for each of the plurality of combination patterns. Further, image recognition apparatus 100 includes an arithmetic computation unit 132 configured to calculate an addition value by adding the co-occurrence feature value calculated for each of the plurality of blocks for each of the plurality of combination patterns, a statistical data generation unit 140 configured to generate statistical data from the addition value. Further, image recognition apparatus 100 includes an image recognition computation unit configured to define a window having a predetermined size for the image and recognize whether or not a predetermined image is included in the window based on the statistical data within the window.

公开(公告)号：US20190065947A1

公开(公告)日：2019-02-28

申请号：US16035010

申请日：2018-07-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi NAKAMURA ,  Akira UTAGAWA ,  Shigeru MATSUO

IPC: G06N3/08 ,  G06K9/46 ,  G06N3/04

Abstract: A semiconductor device includes an image recognition device having a convolution arithmetic processing circuit. The convolution arithmetic processing circuit includes a coefficient register where coefficients of an integration coefficient table are set, a product calculation circuit that calculates products of an input image and the coefficients, a channel register where a channel number of the integration coefficient table is set, a channel selection circuit that selects an output destination of a cumulative addition arithmetic operation on the basis of the channel number, and a plurality of output registers that store a result of the cumulative addition arithmetic operation. The integration coefficient table is a table where a plurality of input coefficient tables are integrated and the integration coefficient table has a size of N×N. The product calculation circuit can calculate data of N×N all at once.