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    SEMICONDUCTOR DEVICE
    1.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240054083A1

    公开(公告)日：2024-02-15

    申请号：US18336215

    申请日：2023-06-16

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kazuaki TERASHIMA ,  Isao NAGAYOSHI ,  Atsushi NAKAMURA

    IPC: G06F13/16 ,  G06F13/28 ,  G06F7/544

    CPC classification number: G06F13/1673 ,  G06F13/28 ,  G06F7/5443

    Abstract: A semiconductor device capable of shortening processing time of a neural network is provided. The memory stores a compressed weight parameter. A plurality of multiply accumulators perform a multiply-accumulation operation to a plurality of pixel data and a plurality of weight parameters. A decompressor restores the compressed weight parameter stored in the memory to a plurality of weight parameters. A memory for weight parameter stores the plurality of weight parameters restored by the decompressor. The DMA controller transfers the plurality of weight parameters from the memory to the memory for weight parameter via the decompressor. A sequence controller writes down the plurality of weight parameters stored in the memory for weight parameter to a weight parameter buffer at write timing.

    SEMICONDUCTOR DEVICE
    4.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230376415A1

    公开(公告)日：2023-11-23

    申请号：US18186476

    申请日：2023-03-20

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kazuaki TERASHIMA ,  Atsushi NAKAMURA ,  Yonghua WANG

    IPC: G06F12/08 ,  G06F7/523 ,  G06F7/50

    CPC classification number: G06F12/08 ,  G06F7/523 ,  G06F7/50 ,  G06F2213/28

    Abstract: A semiconductor device capable of reducing power consumption is provided. A group controller detects a zero weight parameter having a zero value among “n×m” weight parameters to be transferred to a weight parameter buffer. Then, when receiving the zero weight parameter as its input, the group controller exchanges the “n×m” weight parameters to be transferred to the weight parameter buffer so that all multiplication results of the “n” multipliers included in a target multiplier group that is one of the “m” multiplier groups are zero. The group controller controls the target multiplier group to be disabled, and exchanges the “n×m” pixel data to be transferred to the data input buffer, based on the exchange of the “n×m” weight parameters.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220398441A1

    公开(公告)日：2022-12-15

    申请号：US17345368

    申请日：2021-06-11

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kazuaki TERASHIMA ,  Isao NAGAYOSHI ,  Atsushi NAKAMURA

    IPC: G06N3/063 ,  G06F13/20 ,  G06F7/544 ,  G06F7/523 ,  G06F7/50

    Abstract: A semiconductor device executes the processing of a neural network. The memory MEM1 holds a plurality of pixel values and j compressed weighting factors. The decompressor DCMP restores the j compressed weighting factors to the uncompressed k (k≥j) weighting factors. The DMA controller DMAC1 reads the j compressed weighting factors from the memory MEM1 and transfers them to the decompressor DCMP. The n (n>k) accumulators in the accumulator unit ACCU multiply a plurality of pixel values and k uncompressed weighting factor to accumulate and add the multiplication results to the time series. A switch circuit SW1 provided between the decompressor DCMP and the accumulator unit ACCU transfers the k uncompressed weighting factors restored by the decompressor DCMP to n accumulators based on the correspondence represented by the identifier.

    SEMICONDUCTOR DEVICE AND IMAGE RECOGNITION SYSTEM
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND IMAGE RECOGNITION SYSTEM 审中-公开

    公开(公告)号：US20190065947A1

    公开(公告)日：2019-02-28

    申请号：US16035010

    申请日：2018-07-13

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Atsushi NAKAMURA ,  Akira UTAGAWA ,  Shigeru MATSUO

    IPC: G06N3/08 ,  G06K9/46 ,  G06N3/04

    Abstract: A semiconductor device includes an image recognition device having a convolution arithmetic processing circuit. The convolution arithmetic processing circuit includes a coefficient register where coefficients of an integration coefficient table are set, a product calculation circuit that calculates products of an input image and the coefficients, a channel register where a channel number of the integration coefficient table is set, a channel selection circuit that selects an output destination of a cumulative addition arithmetic operation on the basis of the channel number, and a plurality of output registers that store a result of the cumulative addition arithmetic operation. The integration coefficient table is a table where a plurality of input coefficient tables are integrated and the integration coefficient table has a size of N×N. The product calculation circuit can calculate data of N×N all at once.

    SEMICONDUCTOR DEVICE AND IMAGE PROCESSING METHOD
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND IMAGE PROCESSING METHOD 有权
    半导体器件和图像处理方法

    公开(公告)号：US20170034471A1

    公开(公告)日：2017-02-02

    申请号：US15290831

    申请日：2016-10-11

    Applicant: Renesas Electronics Corporation

    Inventor： Hiroyuki HAMASAKI ,  Atsushi NAKAMURA ,  Manabu KOIKE ,  Hideaki KIDO ,  Nobuyasu KANEKAWA

    IPC: H04N5/77 ,  G06T1/20 ,  H04N5/265 ,  H04N5/91 ,  H04N5/232 ,  G06T1/60

    CPC classification number: H04N5/77 ,  G06T1/20 ,  G06T1/60 ,  G06T2200/28 ,  H04N5/23229 ,  H04N5/265 ,  H04N5/91

    Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

    Abstract translation: 图像处理装置包括图像处理单元，其从一个图像数据计算两种图像数据并输出计算出的图像数据;数据组合单元，其组合从图像处理单元提供的两种数据，并将该组合数据输出到 一个终端，输出缓冲器，根据从用于仲裁总线的总线仲裁装置提供的指令调整组合数据的输出定时;以及数据分配单元，其以从形式输出从输出缓冲器输出到总线的组合数据 或者分发组合数据，并根据外部组合分配指令将分布式数据输出到总线。

    SEMICONDUCTOR DEVICE
    9.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230297528A1

    公开(公告)日：2023-09-21

    申请号：US18152582

    申请日：2023-01-10

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kazuaki TERASHIMA ,  Atsushi NAKAMURA ,  Rajesh GHIMIRE

    IPC: G06F13/28 ,  G06F13/16 ,  G06F7/544

    CPC classification number: G06F13/28 ,  G06F13/1689 ,  G06F7/5443

    Abstract: A semiconductor device capable of preventing a sharp variation in current consumption in neural network processing is provided. A dummy circuit outputs dummy data to at least one or more of n number of MAC circuits and causes the at least one or more of n number of MAC circuits to perform a dummy calculation and to output dummy output data. An output-side DMA controller transfers pieces of normal output data from the n number of MAC circuits to a memory, by use of n number of channels, respectively, and does not transfer the dummy output data to the memory. In this semiconductor device, the at least one or more of n number of MAC circuits perform the dummy calculation in a period from a timing at which the output-side DMA controller ends data transfer to the memory to a timing at which the input-side DMA controller starts data transfer from the memory.

    IMAGE RECOGNITION APPARATUS, IMAGE RECOGNITION SYSTEM, AND IMAGE RECOGNITION METHOD
    10.
    发明申请
    IMAGE RECOGNITION APPARATUS, IMAGE RECOGNITION SYSTEM, AND IMAGE RECOGNITION METHOD 审中-公开

    公开(公告)号：US20180039858A1

    公开(公告)日：2018-02-08

    申请号：US15600741

    申请日：2017-05-21

    Applicant: Renesas Electronics Corporation

    Inventor： Akira UTAGAWA ,  Takaaki SATO ,  Atsushi NAKAMURA ,  Manabu KOIKE ,  Masaya ITOH

    IPC: G06K9/62 ,  G06F17/30 ,  G06K9/46

    CPC classification number: G06K9/6212 ,  G06F16/5838 ,  G06K9/00791 ,  G06K9/4609 ,  G06K9/4642 ,  G06K9/4652 ,  G06K9/6255 ,  G06K9/68 ,  G06K2009/4666 ,  G06K2009/485

    Abstract: An image recognition apparatus 100 includes a gradient feature computation unit 120 configured to calculate, from an image divided into a plurality of blocks, gradient feature values for each of the plurality of blocks, a combination pattern storage unit 160 configured to store a plurality of combination patterns of the gradient feature values, and a co-occurrence feature computation unit 131 configured to calculate a co-occurrence feature value in a plurality of blocks for each of the plurality of combination patterns. Further, image recognition apparatus 100 includes an arithmetic computation unit 132 configured to calculate an addition value by adding the co-occurrence feature value calculated for each of the plurality of blocks for each of the plurality of combination patterns, a statistical data generation unit 140 configured to generate statistical data from the addition value. Further, image recognition apparatus 100 includes an image recognition computation unit configured to define a window having a predetermined size for the image and recognize whether or not a predetermined image is included in the window based on the statistical data within the window.

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