公开(公告)号：US11824113B2

公开(公告)日：2023-11-21

申请号：US17901416

申请日：2022-09-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Machiko Sato ,  Akihiro Shimomura

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/1095 ,  H01L29/66734

Abstract: A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.

公开(公告)号：US12211932B2

公开(公告)日：2025-01-28

申请号：US18484710

申请日：2023-10-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Machiko Sato ,  Akihiro Shimomura

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.