公开(公告)号：US11824113B2

公开(公告)日：2023-11-21

申请号：US17901416

申请日：2022-09-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Machiko Sato ,  Akihiro Shimomura

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/1095 ,  H01L29/66734

Abstract: A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.

公开(公告)号：US09385230B2

公开(公告)日：2016-07-05

申请号：US14804819

申请日：2015-07-21

Applicant: Renesas Electronics Corporation

Inventor： Akihiro Shimomura ,  Yutaka Akiyama ,  Saya Shimomura ,  Yasutaka Nakashiba

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/808 ,  H01L29/40 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083

Abstract: A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.

Abstract translation: 一种半导体器件，包括第一导体层，形成在第一导体层上的第二导体层，形成在第二导体层上的第三导体层，通过第三导体层并形成在第二导体层中的栅极沟槽， 形成在栅极沟槽的内壁上的第一绝缘膜，形成在栅极沟槽的内壁上的第二绝缘膜，形成在栅极沟槽中的第一掩埋导体层，形成在栅极沟槽中的栅电极，第四绝缘膜 在第一掩埋导体层的下端形成的第二导电类型的导体层和栅极沟槽的下端，以及形成在第三导体层上的第一导电类型的第五导电层。 第一绝缘膜比第二绝缘膜厚。

公开(公告)号：US12211932B2

公开(公告)日：2025-01-28

申请号：US18484710

申请日：2023-10-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Machiko Sato ,  Akihiro Shimomura

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.

公开(公告)号：US12125905B2

公开(公告)日：2024-10-22

申请号：US16905071

申请日：2020-06-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshinori Kaya ,  Katsumi Eikyu ,  Akihiro Shimomura ,  Hiroshi Yanagigawa ,  Kazuhisa Mori

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7828 ,  H01L29/7831 ,  H01L29/0692

Abstract: To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.

公开(公告)号：US20160336443A1

公开(公告)日：2016-11-17

申请号：US15079338

申请日：2016-03-24

Applicant: Renesas Electronics Corporation

Inventor： Wataru Sumida ,  Akihiro Shimomura

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a vertical MOSFET in which bottom portions of each gate electrode formed in a ditch are extended toward the drain region, the on resistance is reduced while preventing voltage resistance reduction and switching speed reduction caused by a capacitance increase between the gate and drain. A vertical MOSFET includes first ditches, second ditches, and gate electrodes. The first ditches are formed in an upper surface portion of an epitaxial layer formed over a semiconductor substrate and extend in a second direction extending along a main surface of the semiconductor substrate. The second ditches are formed in bottom surface portions of each of the first ditches and are arranged in the second direction. The gate electrodes are formed in the first ditches and second ditches. The gate electrodes formed in the first ditches include lower electrodes arranged in the second direction.

Abstract translation: 在形成沟槽的各栅电极的底部朝向漏极区域延伸的垂直MOSFET中，导通电阻降低，同时防止由栅极和漏极之间的电容增加引起的电阻降低和开关速度降低。 垂直MOSFET包括第一沟道，第二沟道和栅电极。 第一沟槽形成在形成在半导体衬底上的外延层的上表面部分中，并沿着沿着半导体衬底的主表面延伸的第二方向延伸。 第二沟槽形成在每个第一沟槽的底表面部分中并且沿第二方向布置。 栅电极形成在第一沟渠和第二沟渠中。 形成在第一沟槽中的栅电极包括沿第二方向布置的下电极。

公开(公告)号：US10170556B2

公开(公告)日：2019-01-01

申请号：US15797519

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Wataru Sumida ,  Akihiro Shimomura

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor device manufacturing method includes preparing a semiconductor substrate of a first conductivity type, forming a semiconductor layer of the first conductivity type over a main surface of the semiconductor substrate, forming a plurality of first ditches in an upper surface portion of the semiconductor layer such that the first ditches are arranged in a first direction extending along an upper surface of the semiconductor substrate, forming a plurality of second ditches in bottom surface portions of each of the first ditches such that the second ditches are arranged in a second direction perpendicular to the first direction, and covering a side wall of each of the first ditches with a first insulating film and a side wall and a bottom surface of each of the second ditches with a second insulating film thicker than the first insulating film.

公开(公告)号：US20180047811A1

公开(公告)日：2018-02-15

申请号：US15797519

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Wataru SUMIDA ,  Akihiro Shimomura

IPC: H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device manufacturing method includes preparing a semiconductor substrate of a first conductivity type, forming a semiconductor layer of the first conductivity type over a main surface of the semiconductor substrate, forming a plurality of first ditches in an upper surface portion of the semiconductor layer such that the first ditches are arranged in a first direction extending along an upper surface of the semiconductor substrate, forming a plurality of second ditches in bottom surface portions of each of the first ditches such that the second ditches are arranged in a second direction perpendicular to the first direction, and covering a side wall of each of the first ditches with a first insulating film and a side wall and a bottom surface of each of the second ditches with a second insulating film thicker than the first insulating film.

公开(公告)号：US09117903B2

公开(公告)日：2015-08-25

申请号：US14204145

申请日：2014-03-11

Applicant: Renesas Electronics Corporation

Inventor： Akihiro Shimomura ,  Yutaka Akiyama ,  Saya Shimomura ,  Yasutaka Nakashiba

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/808 ,  H01L29/40 ,  H01L29/739

CPC classification number: H01L29/7827 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083

Abstract: A buried layer of a second conductivity type and a lower layer of a second conductivity type are formed in a drift layer. A boundary insulating film is formed in the boundary between the lateral portion of the buried layer of a second conductivity type and the drift layer. The lower layer of a second conductivity type is in contact with the lower end of the buried layer of a second conductivity type and the lower end of the boundary insulating film. The buried layer of a second conductivity type is electrically connected to a source electrode. A high-concentration layer of a second conductivity type is formed in the surface layer of the buried layer of a second conductivity type.

Abstract translation: 在漂移层中形成第二导电类型的掩埋层和第二导电类型的下层。 边界绝缘膜形成在第二导电类型的掩埋层的横向部分与漂移层之间的边界中。 第二导电类型的下层与第二导电类型的掩埋层的下端和边界绝缘膜的下端接触。 第二导电类型的掩埋层与源电极电连接。 在第二导电类型的掩埋层的表面层中形成第二导电类型的高浓度层。

公开(公告)号：US11557648B2

公开(公告)日：2023-01-17

申请号：US17115204

申请日：2020-12-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi Yanagigawa ,  Katsumi Eikyu ,  Masami Sawada ,  Akihiro Shimomura ,  Kazuhisa Mori

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: In a trench gate type power MOSFET having a super-junction structure, both improvement of a breakdown voltage of a device and reduction of on-resistance are achieved. The trench gate and a column region are arranged so as to be substantially orthogonal to each other in a plan view, and a base region (channel forming region) and the column region are arranged separately in a cross-sectional view.

公开(公告)号：US09837492B2

公开(公告)日：2017-12-05

申请号：US15079338

申请日：2016-03-24

Applicant: Renesas Electronics Corporation

Inventor： Wataru Sumida ,  Akihiro Shimomura

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a vertical MOSFET in which bottom portions of each gate electrode formed in a ditch are extended toward the drain region, the on resistance is reduced while preventing voltage resistance reduction and switching speed reduction caused by a capacitance increase between the gate and drain. A vertical MOSFET includes first ditches, second ditches, and gate electrodes. The first ditches are formed in an upper surface portion of an epitaxial layer formed over a semiconductor substrate and extend in a second direction extending along a main surface of the semiconductor substrate. The second ditches are formed in bottom surface portions of each of the first ditches and are arranged in the second direction. The gate electrodes are formed in the first ditches and second ditches. The gate electrodes formed in the first ditches include lower electrodes arranged in the second direction.