公开(公告)号：US20150221722A1

公开(公告)日：2015-08-06

申请号：US14688997

申请日：2015-04-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Mahito SAWADA ,  Tatsunori KANEOKA ,  Katsuyuki HORITA

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3105 ,  H01L21/76205 ,  H01L21/76229 ,  H01L27/088

Abstract: To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.

Abstract translation: 提供一种具有能够阻碍对半导体元件的电特性的不利影响的元件隔离结构的半导体器件及其制造方法。 留在具有相对窄的宽度的浅沟槽隔离中的第一氧化硅膜的厚度比留在具有较宽宽度的浅沟槽隔离中的第一氧化硅膜薄。 通过HDP-CVD法具有相对高的压缩应力的第二氧化硅膜（上层）通过第一氧化硅膜的厚度较薄地层叠在下层的第一氧化硅膜上。 最终形成在具有相对窄的宽度的浅沟槽隔离中的元件隔离氧化膜的压缩应力被更强化。

公开(公告)号：US20130149837A1

公开(公告)日：2013-06-13

申请号：US13758802

申请日：2013-02-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Mahito SAWADA ,  Tatsunori KANEOKA ,  Katsuyuki HORITA

IPC: H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3105 ,  H01L21/76205 ,  H01L21/76229 ,  H01L27/088

Abstract: To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.

Abstract translation: 提供一种具有能够阻碍对半导体元件的电特性的不利影响的元件隔离结构的半导体器件及其制造方法。 留在具有相对窄的宽度的浅沟槽隔离中的第一氧化硅膜的厚度比留在具有较宽宽度的浅沟槽隔离中的第一氧化硅膜薄。 通过HDP-CVD法具有相对高的压缩应力的第二氧化硅膜（上层）通过第一氧化硅膜的厚度较薄地层叠在下层的第一氧化硅膜上。 最终形成在具有相对窄的宽度的浅沟槽隔离中的元件隔离氧化膜的压缩应力被更强化。