公开(公告)号：US20150146477A1

公开(公告)日：2015-05-28

申请号：US14541589

申请日：2014-11-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masaaki IIJIMA ,  Nguyen Thein

IPC: G11C11/4076

CPC classification number: G11C11/4076 ,  G11C7/222

Abstract: In order to solve a problem that a calibration period for generating a signal obtained by delaying a core clock in a programmable manner is overhead in initialization, a clock generation circuit generates a plurality of delayed clocks having different phases by delaying a core clock which is an operation clock of a CPU, and selects a resynchronization clock whose phase is later than and closest to a phase of a data strobe signal from among the generated delayed clocks and the core clock.

Abstract translation: 为了解决用于产生通过以可编程方式延迟核心时钟而获得的信号的校准周期的初始化的开销的问题，时钟产生电路通过延迟核心时钟来产生具有不同相位的多个延迟时钟，该核心时钟是 并且从所生成的延迟时钟和核心时钟中选择相位晚于并且最接近于数据选通信号的相位的再同步时钟。