公开(公告)号：US20130065368A1

公开(公告)日：2013-03-14

申请号：US13671482

申请日：2012-11-07

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Kan YASUI ,  Digh HISAMOTO ,  Tetsuya ISHIMARU ,  Shin-ichiro KIMURA

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

摘要： A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

摘要翻译： 提供了一种制造非易失性半导体存储器件的方法，其克服了由于利用侧壁结构同时形成自对准分裂栅型存储单元而产生的最佳栅极高度的差异而引入的注入离子的问题，以及 一个缩放的MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。