公开(公告)号：US20150249126A1

公开(公告)日：2015-09-03

申请号：US14620401

申请日：2015-02-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hajime KATAOKA ,  Tatsuya SHIROMOTO ,  Tetsuya NITTA

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/761 ,  H01L21/764 ,  H01L23/3171 ,  H01L23/485 ,  H01L23/522 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To provide a semiconductor device having improved performances. A semiconductor substrate has, in the surface layer portion thereof, an n+ type semiconductor region for source and an n+ type semiconductor region for drain separated from each other. The semiconductor substrate has, on the main surface thereof between the n+ type semiconductor region for source and the n+ type semiconductor region for drain, a gate electrode via an insulating film as a gate insulating film. The semiconductor substrate has, in the main surface thereof between the channel formation region below the gate electrode and the n+ type semiconductor region for drain, a LOCOS oxide film and an STI insulating. Of the LOCOS oxide film and the STI insulating film, the LOCOS oxide film is located on the side of the channel formation region and the STI insulating film is on the side of the n+ type semiconductor region DR for drain.

Abstract translation: 提供具有改进性能的半导体器件。 半导体衬底在其表层部分中具有用于源极的n +型半导体区域和用于漏极的n +型半导体区域彼此分离。 半导体衬底在其源极的n +型半导体区域和用于漏极的n +型半导体区域之间的主表面上具有作为栅极绝缘膜的绝缘膜的栅电极。 半导体衬底的主表面在栅电极下方的沟道形成区域和用于漏极的n +型半导体区域之间具有LOCOS氧化物膜和STI绝缘体。 在LOCOS氧化物膜和STI绝缘膜中，LOCOS氧化物膜位于沟道形成区域侧，STI绝缘膜位于用于漏极的n +型半导体区域DR侧。