公开(公告)号：US10043702B2

公开(公告)日：2018-08-07

申请号：US15640564

申请日：2017-07-02

Applicant: Renesas Electronics Corporation

Inventor： Tomohiko Aika

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/308 ,  H01L21/027 ,  H01L21/311 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  G03F7/16 ,  G03F7/24 ,  G03F7/09 ,  G03F7/11

Abstract: A photoresist pattern is not formed in an outer circumferential region from an outer circumferential end of a semiconductor substrate up to 0.5 mm to 3.0 mm, in a process for patterning a silicon oxide film which will serve as a hard mask. A part of the silicon oxide film which is positioned in the outer circumferential region is removed, thereby exposing the semiconductor substrate, in a process for performing an etching process for patterning the silicon oxide film. In the process for performing the etching process for the semiconductor substrate with using the silicon oxide film as an etching mask, the surface of the semiconductor substrate of the outer circumferential region is lowered. Then, a step difference is formed in a position nearer to a chip formation region, in the semiconductor substrate.

公开(公告)号：US10916500B2

公开(公告)日：2021-02-09

申请号：US16523685

申请日：2019-07-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiko Aika ,  Takayuki Igarashi ,  Takehiro Ochi

IPC: H01L23/525 ,  H01L21/8234 ,  H01L27/06

Abstract: Reliability of a semiconductor device is improved. The semiconductor device includes a silicon pattern for a fuse element, a metal silicide layer formed on an upper surface and a side surface of the silicon pattern, a gate electrode for MISFET, and a metal silicide layer formed on an upper surface of the gate electrode. The height from the lower surface of the silicon pattern to the lower end of the metal silicide layer is lower than the height from the lower surface of the gate electrode to the lower end of the metal silicide layer.

公开(公告)号：US09558989B2

公开(公告)日：2017-01-31

申请号：US14796984

申请日：2015-07-10

Applicant: Renesas Electronics Corporation

Inventor： Tomohiko Aika ,  Hajime Suzuki ,  Naoki Fujita

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/823481 ,  H01L27/1203

Abstract: After embedding a silicon oxide film within a second trench that opens in a semiconductor substrate using a silicon nitride film as a hard mask, the silicon oxide film over the silicon nitride film is polished, and then, wet etching is performed before a step for removing the silicon nitride film, and thereby the upper surface of the silicon oxide film within a first trench opened in the silicon nitride film is retreated.

Abstract translation: 在使用氮化硅膜作为硬掩模在半导体衬底中打开的第二沟槽中埋入氧化硅膜之后，对氮化硅膜上的氧化硅膜进行抛光，然后在除去步骤之前进行湿式蚀刻 在氮化硅膜中开放的第一沟槽内的氧化硅膜的上表面被退回，

公开(公告)号：US20160013092A1

公开(公告)日：2016-01-14

申请号：US14796984

申请日：2015-07-10

Applicant: Renesas Electronics Corporation

Inventor： Tomohiko Aika ,  Hajime Suzuki ,  Naoki Fujita

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/823481 ,  H01L27/1203

Abstract: After embedding a silicon oxide film within a second trench that opens in a semiconductor substrate using a silicon nitride film as a hard mask, the silicon oxide film over the silicon nitride film is polished, and then, wet etching is performed before a step for removing the silicon nitride film, and thereby the upper surface of the silicon oxide film within a first trench opened in the silicon nitride film is retreated.

Abstract translation: 在使用氮化硅膜作为硬掩模在半导体衬底中打开的第二沟槽中埋入氧化硅膜之后，对氮化硅膜上的氧化硅膜进行抛光，然后在除去步骤之前进行湿式蚀刻 在氮化硅膜中开放的第一沟槽内的氧化硅膜的上表面被退回，