公开(公告)号：US20190246475A1

公开(公告)日：2019-08-08

申请号：US16198860

申请日：2018-11-22

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Huan-Chien Yang ,  Tsung-Wei Huang ,  Hui-Wen Cheng ,  Shui-Mu Lin

IPC: H05B37/02 ,  G11C27/02

CPC classification number: H05B37/0209 ,  G11C27/02

Abstract: A light emitting device driver circuit includes: a power conversion circuit, an error amplifier circuit, a sample-and-hold circuit, a load current generation circuit and a feed-forward capacitor. When the light emitting device driver circuit is in a disable phase, the sample-and-hold circuit connects a feedback signal with a second reference voltage and the sample-and-hold circuit disconnects the feedback signal from a load node, whereby the feed-forward capacitor samples a sample voltage and holds it after the disable phase transits to an enable phase. In the enable phase, the sample-and-hold circuit disconnects the feedback signal from the second reference voltage and the sample-and-hold circuit connects the feedback signal with the load node, so that during a predetermined period following the transition, there is a sufficient difference between two input terminals of the error amplifier circuit so that the load current is raised to a desired current level within the predetermined period.

公开(公告)号：US10356878B1

公开(公告)日：2019-07-16

申请号：US16198860

申请日：2018-11-22

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Huan-Chien Yang ,  Tsung-Wei Huang ,  Hui-Wen Cheng ,  Shui-Mu Lin

IPC: G11C27/02 ,  H05B37/02

CPC classification number: H05B37/0209 ,  G11C27/02

Abstract: A light emitting device driver circuit includes: a power conversion circuit, an error amplifier circuit, a sample-and-hold circuit, a load current generation circuit and a feed-forward capacitor. When the light emitting device driver circuit is in a disable phase, the sample-and-hold circuit connects a feedback signal with a second reference voltage and the sample-and-hold circuit disconnects the feedback signal from a load node, whereby the feed-forward capacitor samples a sample voltage and holds it after the disable phase transits to an enable phase. In the enable phase, the sample-and-hold circuit disconnects the feedback signal from the second reference voltage and the sample-and-hold circuit connects the feedback signal with the load node, so that during a predetermined period following the transition, there is a sufficient difference between two input terminals of the error amplifier circuit so that the load current is raised to a desired current level within the predetermined period.