公开(公告)号：US20250142863A1

公开(公告)日：2025-05-01

申请号：US19008676

申请日：2025-01-03

Applicant: ROHM CO., LTD.

Inventor： Hirotaka OTAKE ,  Kentaro CHIKAMATSU

IPC: H10D30/47 ,  H10D30/01 ,  H10D30/67 ,  H10D62/824 ,  H10D62/85 ,  H10D64/64

Abstract: A method for manufacturing nitride semiconductor device includes a second step of forming, on a gate layer material film, a gate electrode film that is a material film of a gate electrode, a third step of selectively etching the gate electrode film to form the gate electrode of a ridge shape, and a fourth step of selectively etching the gate layer material film to form a semiconductor gate layer of a ridge shape with the gate electrode disposed at a width intermediate portion of a front surface thereof. The third step includes a first etching step for forming a first portion from an upper end to a thickness direction intermediate portion of the gate electrode and a second etching step being a step differing in etching condition from the first etching step and being for forming remaining second portion of the gate electrode.

公开(公告)号：US20200176400A1

公开(公告)日：2020-06-04

申请号：US16780514

申请日：2020-02-03

Applicant: ROHM CO., LTD.

Inventor： Kentaro CHIKAMATSU ,  Koshun SAITO ,  Kenichi YOSHIMOCHI

IPC: H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

Abstract: A semiconductor device includes a lead frame, a transistor, and an encapsulation resin. The lead frame includes a drain frame, a source frame, and a gate frame. The drain frame includes drain frame fingers. The source frame includes source frame fingers. The drain frame fingers and the source frame fingers are alternately arranged in a first direction and include overlapping portions as viewed from a first direction. In a region where each drain frame finger overlaps the source frame fingers as viewed in the first direction, at least either one of the drain frame fingers and the source frame fingers are not exposed from the back surface of the encapsulation resin.

公开(公告)号：US20230387285A1

公开(公告)日：2023-11-30

申请号：US18364479

申请日：2023-08-03

Applicant: ROHM CO., LTD.

Inventor： Kentaro CHIKAMATSU

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/40

CPC classification number: H01L29/7786 ,  H01L29/66462 ,  H01L29/2003 ,  H01L29/402

Abstract: A nitride semiconductor device includes an electron transit layer, an electron supply layer, a gate layer, a gate electrode, an insulation layer covering the electron supply layer, the gate layer, and the gate electrode and including a first opening and a second opening, a source electrode, and a drain electrode. The source electrode includes a source field plate covering the insulation layer and including an end located between the second opening and the gate layer in plan view. The insulation layer includes a first insulation layer part and a second insulation layer part. The first insulation layer part is disposed on the electron supply layer in contact with the drain electrode and has a first thickness. The second insulation layer part is disposed on the gate electrode in contact with the source field plate and has a second thickness. The second thickness is greater than the first thickness.

公开(公告)号：US20230043312A1

公开(公告)日：2023-02-09

申请号：US17787945

申请日：2021-01-15

Applicant: ROHM CO., LTD.

Inventor： Hirotaka OTAKE ,  Kentaro CHIKAMATSU

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/66

Abstract: A method for manufacturing nitride semiconductor device includes a second step of forming, on a gate layer material film, a gate electrode film that is a material film of a gate electrode, a third step of selectively etching the gate electrode film to form the gate electrode 22 of a ridge shape, and a fourth step of selectively etching the gate layer material film to form a semiconductor gate layer 21 of a ridge shape with the gate electrode 22 disposed at a width intermediate portion of a front surface thereof. The third step includes a first etching step for forming a first portion 22A from an upper end to a thickness direction intermediate portion of the gate electrode 22 and a second etching step being a step differing in etching condition from the first etching step and being for forming a remaining second portion 22B of the gate electrode.

公开(公告)号：US20160218203A1

公开(公告)日：2016-07-28

申请号：US15003772

申请日：2016-01-21

Applicant: ROHM CO., LTD.

Inventor： Kentaro CHIKAMATSU ,  Taketoshi TANAKA ,  Minoru AKUTSU

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/66462

Abstract: A semiconductor device comprises a Group III nitride semiconductor lamination structure including a hetero-junction; an insulating layer formed on the Group III nitride semiconductor lamination structure, the insulating layer including a gate opening portion extending to the Group III nitride semiconductor lamination structure; a gate insulating film configured to cover a bottom portion and a side portion of the gate opening portion; a gate electrode formed on the gate insulating film in the gate opening portion; a source electrode and a drain electrode disposed in a spaced-apart relationship with the gate electrode to sandwich the gate electrode and electrically connected to the Group III nitride semiconductor lamination structure; and a conductive layer embedded in the insulating layer between the gate electrode and the drain electrode and insulated from the gate electrode by the gate insulating film, the conductive layer electrically connected to the source electrode.

Abstract translation: 半导体器件包括包含异质结的III族氮化物半导体层叠结构; 形成在所述III族氮化物半导体层叠结构上的绝缘层，所述绝缘层包括延伸至所述III族氮化物半导体层叠结构的栅极开口部; 栅极绝缘膜，被配置为覆盖所述栅极开口部的底部和侧部; 形成在栅极开口部的栅极绝缘膜上的栅电极; 源极电极和漏电极，与栅电极间隔设置，夹着栅电极，与III族氮化物半导体层叠结构电连接; 以及导电层，其被嵌入在栅电极和漏电极之间的绝缘层中，并且通过栅极绝缘膜与栅电极绝缘，导电层与源电极电连接。

公开(公告)号：US20240266258A1

公开(公告)日：2024-08-08

申请号：US18636274

申请日：2024-04-16

Applicant: ROHM CO., LTD.

Inventor： Kentaro CHIKAMATSU

IPC: H01L23/482 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L23/4824 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786

Abstract: A semiconductor device is provided with: a source wiring electrically coupled to the source electrode of a transistor; a drain wiring electrically coupled to the drain electrode of the transistor; a source pad electrically coupled to the source wiring; and, a drain pad electrically coupled to the drain wiring. The source wiring includes a first source wiring section and a second source wiring section having a width greater than that of the first source wiring section. The drain wiring includes a first drain wiring section and a second drain wiring section having a width greater than that of the first drain wiring section. The source pad at least partially overlaps the second drain wiring section in plan view. The drain pad at least partially overlaps the second source wiring section in plan view.

公开(公告)号：US20230326846A1

公开(公告)日：2023-10-12

申请号：US18318423

申请日：2023-05-16

Applicant: ROHM CO., LTD.

Inventor： Minoru AKUTSU ,  Kentaro CHIKAMATSU

IPC: H01L23/522 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L23/5222 ,  H01L29/66462 ,  H01L29/7787

Abstract: A semiconductor device 1 has an electrode structure that includes source electrodes 3, a gate electrode 4, and drain electrodes 5 disposed on a semiconductor laminated structure 2 and extending in parallel to each other and in a predetermined first direction and a wiring structure that includes source wirings 9, drain wirings 10, and gate wirings 11 disposed on the electrode structure and extending in parallel to each other and in a second direction orthogonal to the first direction. The source wirings 9, the drain wirings 10, and the gate wirings 11 are electrically connected to the source electrodes 3, the drain electrodes 5, and the gate electrode 4, respectively. The semiconductor device 1 includes a conductive film 8 disposed between the gate electrode 4 and the drain wirings 10 and being electrically connected to the source electrodes 3.

公开(公告)号：US20200287034A1

公开(公告)日：2020-09-10

申请号：US16884939

申请日：2020-05-27

Applicant: ROHM CO., LTD.

Inventor： Kentaro CHIKAMATSU

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/40 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device is provided with, a group-III nitride semiconductor layered structure that includes a heterojunction, an insulating layer which has a gate opening that reaches the group-III nitride semiconductor layered structure and which is disposed on the group-III nitride semiconductor layered structure, a gate insulating film that covers the bottom and the side of the gate opening, a gate electrode defined on the gate insulating film inside the gate opening, a source electrode and a drain electrode which are disposed to be spaced apart from the gate electrode so as to sandwich the gate electrode, a first conductive layer embedded in the insulating layer between the gate electrode and the drain electrode, and a second conductive layer that is embedded in the insulating layer above the first conductive layer in a region closer to the drain electrode side than the first conductive layer.

公开(公告)号：US20230005840A1

公开(公告)日：2023-01-05

申请号：US17930991

申请日：2022-09-09

Applicant: ROHM CO., LTD.

Inventor： Hirotaka OTAKE ,  Kentaro CHIKAMATSU

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor chip includes a front surface and a back surface, a source pad, a drain pad and a gate pad on the front surface; a die pad under the semiconductor chip and bonded to the semiconductor chip; a source lead, electrically connected to the die pad; a drain lead and a gate lead, disposed on a periphery of the die pad; and a sealing resin. A plurality of vias for external connection are formed to connect to the source pad. A first subset of the plurality of vias for external connection is disposed along a first side of the source pad, and a second subset of the plurality of vias for external connection is disposed along a second side of the source pad, wherein the first and second sides are arranged adjacent to each other to form a first edge of the source pad.

公开(公告)号：US20220199820A1

公开(公告)日：2022-06-23

申请号：US17605442

申请日：2020-03-06

Applicant: ROHM CO., LTD.

Inventor： Hirotaka OTAKE ,  Kentaro CHIKAMATSU ,  Minoru AKUTSU ,  Shinya TAKADO

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/812

Abstract: A nitride semiconductor device 1 includes a first nitride semiconductor layer that constitutes an electron transit layer, a second nitride semiconductor layer that is formed on the first nitride semiconductor layer, is larger in bandgap than the first nitride semiconductor layer, and constitutes an electron supply layer, a gate portion that is formed on the second nitride semiconductor layer, and a source electrode and a drain electrode that, on the second nitride semiconductor layer, are opposingly disposed across the gate portion. The gate portion includes a third nitride semiconductor layer of a ridge shape that is formed on the second nitride semiconductor layer and contains an acceptor type impurity and a gate electrode that is formed on the third nitride semiconductor layer. A film thickness of the third nitride semiconductor layer is greater than 100 nm.