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    AUTOMATIC GAIN CONTROL ACQUISITION IN TIME DIVISION DUPLEX SYSTEMS
    1.
    发明申请
    AUTOMATIC GAIN CONTROL ACQUISITION IN TIME DIVISION DUPLEX SYSTEMS 有权
    时分双工系统中的自动增益控制获取

    公开(公告)号：US20110243038A1

    公开(公告)日：2011-10-06

    申请号：US13069296

    申请日：2011-03-22

    申请人： Raghu N. Challa ,  Brian Clarke Banister

    发明人： Raghu N. Challa ,  Brian Clarke Banister

    IPC分类号： H04J3/00

    CPC分类号： H03G3/3078

    摘要： In embodiments, user equipment (UE) is configured to acquire automatic gain control (AGC) of an analog RF front end by maintaining a plurality of M×N AGC loops in which the output of the power detector drives input of a gain state machine after a predetermined delay. Each of the loops corresponds to a different periodic set of tasks of (1/M) subframe in length. In each of the loops, the gain is determined by a power measurement taken ((M×N)+1) tasks ago. A synchronization signal, such as a Primary Synchronization Signal, occurs early in Time Division Duplex (TDD) subframes that follow selected downlink subframes. The periodicity of the selected subframes is N. This allows the UE to converge on proper AGC gain for downlink subframes through a relatively short search, such as a binary search. The UE can then decode the synchronization signal and acquire network timing.

    摘要翻译： 在实施例中，用户设备（UE）被配置为通过维持多个M×N个AGC环路来获取模拟RF前端的自动增益控制（AGC），其中功率检测器的输出驱动增益状态机的输入驱动增益状态机的输入， 预定的延迟。 每个循环对应于长度为（1 / M）子帧的不同周期性任务集合。 在每个循环中，增益由以前进行的功率测量（（M×N）+1）任务确定。 诸如主同步信号的同步信号早于在选择的下行链路子帧之后的时分双工（TDD）子帧中。 所选择的子帧的周期为N.这允许UE通过相对较短的搜索（例如二进制搜索）收敛于针对下行链路子帧的适当的AGC增益。 然后，UE可以对同步信号进行解码并获取网络定时。

    Automatic gain control acquisition in time division duplex systems
    2.
    发明授权
    Automatic gain control acquisition in time division duplex systems 有权
    在时分双工系统中自动增益控制采集

    公开(公告)号：US08780768B2

    公开(公告)日：2014-07-15

    申请号：US13069296

    申请日：2011-03-22

    申请人： Raghu N. Challa ,  Brian Clarke Banister

    发明人： Raghu N. Challa ,  Brian Clarke Banister

    IPC分类号： H04J3/06

    CPC分类号： H03G3/3078

    摘要： In embodiments, user equipment (UE) is configured to acquire automatic gain control (AGC) of an analog RF front end by maintaining a plurality of M×N AGC loops in which the output of the power detector drives input of a gain state machine after a predetermined delay. Each of the loops corresponds to a different periodic set of tasks of (1/M) subframe in length. In each of the loops, the gain is determined by a power measurement taken ((M×N)+1) tasks ago. A synchronization signal, such as a Primary Synchronization Signal, occurs early in Time Division Duplex (TDD) subframes that follow selected downlink subframes. The periodicity of the selected subframes is N. This allows the UE to converge on proper AGC gain for downlink subframes through a relatively short search, such as a binary search. The UE can then decode the synchronization signal and acquire network timing.

    摘要翻译： 在实施例中，用户设备（UE）被配置为通过维持多个M×N个AGC环路来获取模拟RF前端的自动增益控制（AGC），其中功率检测器的输出驱动增益状态机的输入驱动增益状态机的输入， 预定的延迟。 每个循环对应于长度为（1 / M）子帧的不同周期性任务集合。 在每个循环中，增益由以前进行的功率测量（（M×N）+1）任务确定。 诸如主同步信号的同步信号早于在选择的下行链路子帧之后的时分双工（TDD）子帧中。 所选择的子帧的周期为N.这允许UE通过相对较短的搜索（例如二进制搜索）收敛于针对下行链路子帧的适当的AGC增益。 然后，UE可以对同步信号进行解码并获取网络定时。

    Multi-stage interference suppression
    3.
    发明授权
    Multi-stage interference suppression 失效
    多级干扰抑制

    公开(公告)号：US08619928B2

    公开(公告)日：2013-12-31

    申请号：US12553848

    申请日：2009-09-03

    申请人： Farrokh Abrishamkar ,  Divaydeep Sikri ,  Raghu N. Challa ,  Bahadir Canpolat

    发明人： Farrokh Abrishamkar ,  Divaydeep Sikri ,  Raghu N. Challa ,  Bahadir Canpolat

    IPC分类号： H04B1/10

    CPC分类号： H04L25/0328 ,  H04L25/0202 ,  H04L25/03286 ,  H04L25/03292 ,  H04L25/03299 ,  H04L2025/03726

    摘要： A multi-stage interference suppression receiver includes a short equalizer section configured to operate on a first portion of a received signal received over a channel to produce a first equalized signal and a first estimate of the channel, a channel estimator section configured to operate on the first equalized signal to produce a second equalized signal, the channel estimator section comprising a linear estimator and a non-linear estimator, a long equalizer section configured to operate on a second portion of the received signal to produce a first estimate of symbols in the received signal and a second estimate of the channel and an interference canceller section configured to operate on the first estimate of symbols in the received signal to generate a second estimate of symbols in the received signal based on, at least in part, the second estimate of the channel.

    摘要翻译： 多级干扰抑制接收机包括短均衡器部分，其被配置为对通过信道接收的接收信号的第一部分进行操作以产生第一均衡信号和信道的第一估计，信道估计器部分被配置为在 第一均衡信号以产生第二均衡信号，所述信道估计器部分包括线性估计器和非线性估计器，长均衡器部分，被配置为在所接收的信号的第二部分上进行操作，以产生接收到的符号的第一估计值 信号和信道的第二估计以及干扰消除器部分，被配置为在接收信号中对符号的第一估计进行操作，以至少部分地基于接收信号的第二估计来生成接收信号中的符号的第二估计 渠道。

    Multiple stage fourier transform apparatus, processes, and articles of manufacture
    4.
    发明授权
    Multiple stage fourier transform apparatus, processes, and articles of manufacture 有权
    多级傅里叶变换装置，工艺和制品

    公开(公告)号：US08218426B2

    公开(公告)日：2012-07-10

    申请号：US12408363

    申请日：2009-03-20

    申请人： Hemanth Sampath ,  Kaushik Ghosh ,  Raghu N. Challa ,  Sameer Vermani

    发明人： Hemanth Sampath ,  Kaushik Ghosh ,  Raghu N. Challa ,  Sameer Vermani

    IPC分类号： H04J11/00

    CPC分类号： H04L27/265 ,  G06F17/142 ,  H04L27/263

    摘要： In embodiments, a fast Fourier transform (FFT) engine includes a series of stages, each stage containing a butterfly and a data normalization device configured to scale output of the stage's butterfly. The scaling factors are adjusted, for example, periodically or on as-needed basis, so that the dynamic range of the butterflies and the buffers is increased for a given bit-width, or the bit-width of these devices is decreased for the same dynamic range. Additionally, bit-width of other buffer(s) is decreased because of the scaling of the data.

    摘要翻译： 在实施例中，快速傅里叶变换（FFT）引擎包括一系列级，每级包含蝴蝶和配置成缩放舞台蝴蝶的输出的数据归一化装置。 比例因子例如可以周期性地或根据需要进行调整，使得蝴蝶和缓冲器的动态范围在给定位宽度上增加，或者这些装置的位宽减小 动态范围。 此外，由于数据的缩放，其他缓冲区的位宽被减小。

    ARCHITECTURE TO HANDLE CONCURRENT MULTIPLE CHANNELS
    7.
    发明申请
    ARCHITECTURE TO HANDLE CONCURRENT MULTIPLE CHANNELS 有权
    构建多个通道的通道

    公开(公告)号：US20090245435A1

    公开(公告)日：2009-10-01

    申请号：US12413069

    申请日：2009-03-27

    申请人： Raghu N. Challa ,  Hemanth Sampath ,  Ali RostamPisheh

    发明人： Raghu N. Challa ,  Hemanth Sampath ,  Ali RostamPisheh

    IPC分类号： H04L27/06

    CPC分类号： H04L1/0045 ,  H03M13/2957 ,  H03M13/6566 ,  H04L5/0007 ,  H04L27/2647

    摘要： An apparatus and method for enhanced downlink processing of received channels in a mobile communications system is described, containing a buffer for control data and traffic data, a demapper engine with at least two independently operating demappers for demapping the control and traffic data, a log-likelihood-ratio (LLR) buffer for supporting memory segments accessible by the demapper engine, a decoder engine containing decoders, each of the decoders operating on data from selected memory segment(s) of the LLR buffer, and an arbitrator providing control of at least one of the demapper engine, LLR buffer, and decoder engine. At least one of the decoders is suited for decoding control data and another one of the decoders is suited for decoding traffic data. By partitioning the decoding as such, an increase in downlink throughput can be obtained.

    摘要翻译： 描述了一种用于在移动通信系统中增强接收信道的下行链路处理的装置和方法，其包括用于控制数据和业务数据的缓冲器，具有至少两个独立操作的解映射器的解映射器引擎，用于对所述控制和业务数据进行解映射， 用于支持由解映射器引擎可访问的存储器段的似然比（LLR）缓冲器，包含解码器的解码器引擎，每个解码器对来自所选择的LLR缓冲器的所选存储器段的数据进行操作，以及至少提供至少控制的仲裁器 一个解映射引擎，LLR缓冲区和解码引擎。 解码器中的至少一个适合于解码控制数据，并且解码器中的另一个适合于解码业务数据。 通过分解解码，可以获得下行链路吞吐量的增加。

    Systems and Methods for Approximating Log Likelihood Ratios in a Communication System
    8.
    发明申请
    Systems and Methods for Approximating Log Likelihood Ratios in a Communication System 失效
    在通信系统中近似对数似然比的系统和方法

    公开(公告)号：US20090245433A1

    公开(公告)日：2009-10-01

    申请号：US12406868

    申请日：2009-03-18

    申请人： Raghu N. Challa ,  Hemanth Sampath ,  Sameer Vermani

    发明人： Raghu N. Challa ,  Hemanth Sampath ,  Sameer Vermani

    IPC分类号： H04L27/06

    CPC分类号： H04L25/067 ,  H04L1/0052

    摘要： Systems and methods for computing log likelihood ratios in a communication system are described. A demodulated symbol may be received. A set of scalars may be determined based on a modulation order, a signal-to-noise ratio for the symbol, and a bit of the symbol. At least one log likelihood ratio for the bit may be approximated using a piecewise linear process based on the scalars and the symbol.

    摘要翻译： 描述用于计算通信系统中的对数似然比的系统和方法。 可以接收解调的符号。 可以基于调制阶数，符号的信噪比和符号的位来确定一组标量。 可以使用基于标量和符号的分段线性处理来近似该比特的至少一个对数似然比。

    Systems and methods for approximating log likelihood ratios in a communication system
    10.
    发明授权
    Systems and methods for approximating log likelihood ratios in a communication system 失效
    用于在通信系统中近似对数似然比的系统和方法

    公开(公告)号：US08761316B2

    公开(公告)日：2014-06-24

    申请号：US12406868

    申请日：2009-03-18

    申请人： Raghu N. Challa ,  Hemanth Sampath ,  Sameer Vermani

    发明人： Raghu N. Challa ,  Hemanth Sampath ,  Sameer Vermani

    IPC分类号： H04L27/06

    CPC分类号： H04L25/067 ,  H04L1/0052

    摘要： Systems and methods for computing log likelihood ratios in a communication system are described. A demodulated symbol may be received. A set of scalars may be determined based on a modulation order, a signal-to-noise ratio for the symbol, and a bit of the symbol. At least one log likelihood ratio for the bit may be approximated using a piecewise linear process based on the scalars and the symbol.

    摘要翻译： 描述用于计算通信系统中的对数似然比的系统和方法。 可以接收解调的符号。 可以基于调制阶数，符号的信噪比和符号的位来确定一组标量。 可以使用基于标量和符号的分段线性处理来近似该比特的至少一个对数似然比。