公开(公告)号：US07558136B2

公开(公告)日：2009-07-07

申请号：US11838341

申请日：2007-08-14

申请人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/006 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/5002

摘要： A memory cell having an asymmetric connection for evaluating dynamic stability provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By operating the cell and observing changes in performance caused by the asymmetry, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each crosscoupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.

摘要翻译： 具有用于评估动态稳定性的不对称连接的存储器单元提供了一种用于提高存储器阵列的性能超过当前水平/产量的机制。 通过操作电池并观察由不对称引起的性能变化，可以通过设计和操作环境研究SRAM单元的动态稳定性。 可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。 或者或组合地，可以改变单元的输出处的负载以影响电池的性能。 可以在生产或测试晶片中制造具有至少一个测试单元的存储器阵列，并且可以探测存储器单元的内部节点以提供进一步的信息。

公开(公告)号：US07561483B2

公开(公告)日：2009-07-14

申请号：US11685904

申请日：2007-03-14

申请人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/006 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/5002

摘要： An internally asymmetric method for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.

摘要翻译： 用于评估静态存储单元动态稳定性的内部非对称方法提供了一种提高存储器阵列的性能超越现有水平/产量的机制。 通过改变静态随机存取存储器（SRAM）存储单元的内部对称性，操作单元并观察不对称操作引起的性能变化，可以通过设计和操作环境研究SRAM单元的动态稳定性。 可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。 或者或组合地，可以改变单元的输出处的负载以影响电池的性能。 可以在生产或测试晶片中制造具有至少一个测试单元的存储器阵列，并且可以探测存储器单元的内部节点以提供进一步的信息。

公开(公告)号：US07515491B2

公开(公告)日：2009-04-07

申请号：US11685905

申请日：2007-03-14

申请人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/006 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/5002

摘要： A method for evaluating leakage effects on static memory cell access time provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the states of other static memory cells connected to the same bitline as a static memory cell under test, the effect of leakage on the access time of the cell can be observed. The leakage effects can further be observed while varying the internal symmetry of the memory cell, operating the cell and observing changes in performance caused by the asymmetric operation. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage.

摘要翻译： 用于评估对静态存储器单元访问时间的泄漏影响的方法提供了一种用于提高存储器阵列的性能超过现有水平/产量的机制。 通过改变与被测试的静态存储器单元连接到同一位线的其它静态存储单元的状态，可以观察到泄漏对单元访问时间的影响。 可以进一步观察泄漏效应，同时改变存储器单元的内部对称性，操作电池并观察不对称操作引起的性能变化。 可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。

公开(公告)号：US07483322B2

公开(公告)日：2009-01-27

申请号：US11963794

申请日：2007-12-22

申请人： Rajiv V. Joshi ,  Qiuyi Ye ,  Yuen H. Chan ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Qiuyi Ye ,  Yuen H. Chan ,  Anirudh Devgan

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C29/50012

摘要： A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.

摘要翻译： 用于评估存储单元性能的环形振荡器行电路在实际的存储器电路环境中提供电路延迟和性能测量。 环形振荡器用一行存储器单元实现，并且具有连接到一个或多个位线以及与环形振荡器单元基本相同的其它存储器单元的输出。 可以包括用于提供完全功能的存储器阵列的逻辑，使得当环形振荡器行字线被禁用时，除了环形振荡器单元之外的单元可以用于存储。 形成环形振荡器电路中使用的静态存储单元的各个交叉耦合的逆变器级的一个或两个电源轨可以彼此隔离，以引入电压不对称，从而可以评估电路不对称对延迟的影响。

公开(公告)号：US07301835B2

公开(公告)日：2007-11-27

申请号：US11225652

申请日：2005-09-13

申请人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/006 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/5002

摘要： Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.

公开(公告)号：US07376001B2

公开(公告)日：2008-05-20

申请号：US11250019

申请日：2005-10-13

申请人： Rajiv V. Joshi ,  Qiuyi Ye ,  Yuen H. Chan ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Qiuyi Ye ,  Yuen H. Chan ,  Anirudh Devgan

IPC分类号： G11C11/00

CPC分类号： G11C29/50 ,  G11C29/50012

摘要： A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator implemented in a row of memory cells and having outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells is operated by the method. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.

摘要翻译： 用于评估存储器单元性能的方法在实际存储器电路环境中提供电路延迟和性能测量。 通过该方法操作在一行存储器单元中实现的具有连接到一个或多个位线的输出的环形振荡器以及与环形振荡器单元基本相同的其它存储器单元。 可以包括用于提供完全功能的存储器阵列的逻辑，使得当环形振荡器行字线被禁用时，除了环形振荡器单元之外的单元可以用于存储。 形成环形振荡器电路中使用的静态存储单元的各个交叉耦合的逆变器级的一个或两个电源轨可以彼此隔离，以引入电压不对称，从而可以评估电路不对称对延迟的影响。

公开(公告)号：US07304895B2

公开(公告)日：2007-12-04

申请号：US11225571

申请日：2005-09-13

申请人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

IPC分类号： G11C29/00

CPC分类号： G11C7/12 ,  G11C11/41 ,  G11C29/006 ,  G11C29/50 ,  G11C2029/1204 ,  G11C2029/5002

摘要： Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the bitline pre-charge voltage of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the changes in the bitline voltage, the dynamic stability of the SRAM cell can be studied over designs and operating environments. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. In addition, cell power supply voltages can be split and set to different levels in order to study the effect of cell asymmetry in combination with bitline pre-charge voltage differences.

摘要翻译： 用于评估静态存储单元动态稳定性的位线可变方法和电路为提高存储器阵列的性能提供了超出当前水平/产量的机制。 通过改变静态随机存取存储器（SRAM）存储器单元的位线预充电电压，操作单元并观察由位线电压变化引起的性能变化，可以研究SRAM单元的动态稳定性，并通过设计和 操作环境。 或者或组合地，可以改变单元的输出处的负载以影响电池的性能。 此外，电池电源电压可以分开并设置为不同的电平，以研究电池不对称与位线预充电电压差的结合。

公开(公告)号：US20080319717A1

公开(公告)日：2008-12-25

申请号：US12199161

申请日：2008-08-27

申请人： Rajiv V. Joshi ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Anirudh Devgan

IPC分类号： G06F17/50 ,  G06F17/10

CPC分类号： G06F17/5045 ,  G06F2217/10

摘要： An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels/yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and then sensitivities of each performance variable to each of the circuit parameters are determined. The memory cell design parameters and/or operating conditions of the memory cells are then adjusted in conformity with the sensitivities, resulting in improved memory yield and/or performance. Once a performance level is attained, the sensitivities can then be used to alter the probability distributions of the performance variables to achieve a higher yield. Multiple cell designs can be compared for performance, yield and sensitivity of performance variables to circuit parameters over particular environmental conditions in order to select the best cell design.

摘要翻译： 一种有效的方法和计算机程序，用于建模和改进在过程变化和环境条件之间的记忆性能，为提高存储器阵列的性能提供了超出当前水平/产量的机制。 对于多个存储器性能变量中的每一个执行电路参数子集的统计（蒙特卡罗）分析，然后确定每个性能变量对每个电路参数的灵敏度。 然后根据敏感度调整存储器单元的存储单元设计参数和/或操作条件，从而提高存储器产量和/或性能。 一旦达到性能水平，然后可以使用敏感度来改变性能变量的概率分布，以获得更高的产量。 为了选择最佳的单元设计，可以将多个单元设计与性能变量的性能，产出和灵敏度进行比较，以便在特定的环境条件下对电路参数进行比较。

公开(公告)号：US08001493B2

公开(公告)日：2011-08-16

申请号：US12199161

申请日：2008-08-27

申请人： Rajiv V. Joshi ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Anirudh Devgan

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/10

摘要： An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels/yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and then sensitivities of each performance variable to each of the circuit parameters are determined. The memory cell design parameters and/or operating conditions of the memory cells are then adjusted in conformity with the sensitivities, resulting in improved memory yield and/or performance. Once a performance level is attained, the sensitivities can then be used to alter the probability distributions of the performance variables to achieve a higher yield. Multiple cell designs can be compared for performance, yield and sensitivity of performance variables to circuit parameters over particular environmental conditions in order to select the best cell design.

摘要翻译： 一种有效的方法和计算机程序，用于建模和改进在过程变化和环境条件之间的记忆性能，为提高存储器阵列的性能提供了超出当前水平/产量的机制。 对于多个存储器性能变量中的每一个执行电路参数子集的统计（蒙特卡罗）分析，然后确定每个性能变量对每个电路参数的灵敏度。 然后根据敏感度调整存储器单元的存储单元设计参数和/或操作条件，从而提高存储器产量和/或性能。 一旦达到性能水平，然后可以使用敏感度来改变性能变量的概率分布，以获得更高的产量。 为了选择最佳的单元设计，可以将多个单元设计与性能变量的性能，产出和灵敏度进行比较，以便在特定的环境条件下对电路参数进行比较。

公开(公告)号：US08767501B2

公开(公告)日：2014-07-01

申请号：US13550762

申请日：2012-07-17

申请人： Rajiv V. Joshi ,  Ajay N. Bhoj

发明人： Rajiv V. Joshi ,  Ajay N. Bhoj

IPC分类号： G11C8/10

CPC分类号： G06F12/0864 ,  G06F2212/1021 ,  G11C15/04

摘要： Associative index extended (AIX) caches can be functionally implemented through a reconfigurable decoder that employs programmable line decoding. The reconfigurable decoder features scalability in the number of lines, the number of index extension bits, and the number of banks. The reconfigurable decoder can switch between pure direct mapped (DM) mode and direct mapped-associative index extended (DM-AIX) mode of operation. For banked configurations, the reconfigurable decoder provides the ability to run some banks in DM mode and some other banks in DM-AIX mode. A cache employing this reconfigurable decoder can provide a comparable level of latency as a DM cache with minimal modifications to a DM cache circuitry of an additional logic circuit on a critical signal path, while providing low power operation at low area overhead with SA cache-like miss rates. Address masking and most-recently-used-save replacement policy can be employed with a single bit overhead per line.

摘要翻译： 关联索引扩展（AIX）缓存可以通过采用可编程线解码的可重构解码器进行功能实现。 可重配置解码器具有线路数量的可扩展性，索引扩展位的数量和存储体的数量。 可重构解码器可以在纯直接映射（DM）模式和直接映射关联索引扩展（DM-AIX）操作模式之间切换。 对于组合配置，可重构解码器能够以DM模式运行某些存储区，并以DM-AIX模式运行其他存储区。 采用该可重构解码器的高速缓存器可以提供与DM高速缓存相当的延迟水平，对关键信号路径上的附加逻辑电路的DM高速缓存电路进行最小修改，同时在低区域开销提供具有SA缓存类似的低功率操作 错过率。 地址掩码和最近使用的保存替换策略可以采用每行一个位开销。