公开(公告)号：US5182809A

公开(公告)日：1993-01-26

申请号：US358810

申请日：1989-05-31

申请人： Ralph M. Begun ,  Patrick M. Bland ,  Philip E. Milling

发明人： Ralph M. Begun ,  Patrick M. Bland ,  Philip E. Milling

IPC分类号： G06F12/08

CPC分类号： G06F12/0888

摘要： A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：US5045998A

公开(公告)日：1991-09-03

申请号：US359794

申请日：1989-06-01

申请人： Ralph M. Begun ,  Patrick M. Bland ,  Mark E. Dean

发明人： Ralph M. Begun ,  Patrick M. Bland ,  Mark E. Dean

IPC分类号： G06F12/08

CPC分类号： G06F12/0888

摘要： A microprocessor system employing an 80386 CPU and an 82385 cache controller has the capability of functioning with dynamic bus sizing (where the CPU interacts with devices which may or may not be 32-bits wide), as well as posted write capability. Unfortunately, the two capabilities have the possibility of an incompatibility if a write cycle is posted to a device which cannot transfer 32 bits on a single cycle. The present invention provides logic to overcome this incompatibility. An address decoder is provided to decode the tag portion of an address asserted on a CPU bus to determine if the asserted address is inside or outside a range of addresses which define cacheable devices. Any cacheable device is by definition 32 bits wide and therefore posted writes are allowed only to cacheable devices. Accordingly, the microcomputer system employing the invention posts write cycles to cacheable devices; write cycles to non-cacheable devices are inhibited from being posted.

摘要翻译： 采用80386 CPU和82385高速缓存控制器的微处理器系统具有动态总线大小调整功能（CPU与可能或不是32位宽的设备交互）以及发布的写入功能。 不幸的是，如果将写周期发布到在单个周期内不能传输32位的器件，则这两个功能具有不兼容的可能性。 本发明提供了克服这种不兼容性的逻辑。 提供地址解码器来解码在CPU总线上断言的地址的标签部分，以确定所断言的地址是否在限定可高速缓存设备的地址范围之内或之外。 任何可缓存设备的定义为32位宽，因此发布的写入仅允许可缓存设备。 因此，采用本发明的微计算机系统将写入周期写入可高速缓存的设备; 对不可缓存设备的写周期被禁止发布。

公开(公告)号：US5170481A

公开(公告)日：1992-12-08

申请号：US367828

申请日：1989-06-19

申请人： Ralph M. Begun ,  Patrick M. Bland ,  Mark E. Dean

发明人： Ralph M. Begun ,  Patrick M. Bland ,  Mark E. Dean

IPC分类号： G06F13/36 ,  G06F13/28 ,  G06F13/362

CPC分类号： G06F13/285 ,  G06F13/362

摘要： A logic circit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request signal, drives the processor into a hold state at the appropriate time in the cycle. The logic circuit also includes a "lockbus" feature that, when the processor is not idle, "locks" the microprocessor to the local CPU bus for a predetermined period of time immediately after the processor is released from a hold state.

公开(公告)号：US5450559A

公开(公告)日：1995-09-12

申请号：US771528

申请日：1991-10-07

申请人： Ralph M. Begun ,  Patrick M. Bland ,  Mark E. Dean

发明人： Ralph M. Begun ,  Patrick M. Bland ,  Mark E. Dean

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0886 ,  G06F12/0806

摘要： The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

摘要翻译： 通过抵消CPU地址输出端子和高速缓存控制器的地址输入端子之间的关系并相应地使高速缓存行大小加倍，可以增加由高速缓存控制器支持的高速缓冲存储器的容量。 在某些情况下，额外的逻辑会产生一个隐藏的内存周期，以便从内存中获取等于新行大小的字节数，而不管数据总线的宽度。 隐藏的存储器周期由读取未命中发起，并且进一步的逻辑产生不由CPU产生的存储器地址。 通过禁止READY信号的改变直到完成正常的存储器周期和隐藏的存储器周期，隐藏的存储器周期对于CPU和高速缓存控制器是保持透明的。

公开(公告)号：US5327545A

公开(公告)日：1994-07-05

申请号：US696809

申请日：1991-05-07

申请人： Ralph M. Begun ,  Patrick M. Bland ,  Mark E. Dean

发明人： Ralph M. Begun ,  Patrick M. Bland ,  Mark E. Dean

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0888

摘要： A microcomputer system employing an 80386 CPU and an 82385 cache controller has the capability of functioning with dynamic bus sizing (where the CPU interacts with devices which may or may not be 32-bits wide), as well as posted write capability. Unfortunately, the two capabilities have the possibility of an incompatibility if a write cycle is posted to a device which cannot transfer 32 bits on a single cycle. The present invention provides logic to overcome this incompatibility. An address decoder is provided to decode the tag portion of an address asserted on a CPU local bus to determine if the asserted address is inside or outside a range of addresses which define cacheable devices. Any cacheable device is by definition 32 bits wide and therefore posted writes are allowed only to cacheable devices. Accordingly, the microcomputer system employing the invention posts write cycles to cacheable devices; write cycles to non-cacheable devices are inhibited from being posted.

摘要翻译： 使用80386 CPU和82385高速缓存控制器的微机系统具有动态总线大小调整功能（CPU与可能或不是32位宽的设备交互）以及发布的写入功能。 不幸的是，如果将写周期发布到在单个周期内不能传输32位的器件，则这两个功能具有不兼容的可能性。 本发明提供了克服这种不兼容性的逻辑。 提供地址解码器来解码在CPU本地总线上断言的地址的标签部分，以确定断言的地址是否在限定可高速缓存设备的地址范围之内或之外。 任何可缓存设备的定义为32位宽，因此发布的写入仅允许可缓存设备。 因此，采用本发明的微计算机系统将写入周期写入可高速缓存的设备; 对不可缓存设备的写周期被禁止发布。

公开(公告)号：US5175826A

公开(公告)日：1992-12-29

申请号：US198890

申请日：1988-05-26

申请人： Ralph M. Begun ,  Patrick M. Bland ,  Mark E. Dean

发明人： Ralph M. Begun ,  Patrick M. Bland ,  Mark E. Dean

IPC分类号： G06F12/08

CPC分类号： G06F12/0802

摘要： In an 80386/82385 microcomputer system, the timing requirements placed on non-cache memory components by the 82385 are more stringent than the timing requirements placed on the non-cache memory components by the 80386. The present invention operates on the 82385 cache write enable (CWE) signals, and delays those signals in the event of a read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

公开(公告)号：US5125084A

公开(公告)日：1992-06-23

申请号：US198894

申请日：1988-05-26

申请人： Ralph M. Begun ,  Patrick M. Bland ,  Mark E. Dean

发明人： Ralph M. Begun ,  Patrick M. Bland ,  Mark E. Dean

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3802 ,  G06F12/0888

摘要： Any incompatibility between pipelined operations (such as is available in the 80386) and dynamic bus sizing (allowing the processor to operate with devices of 8-, 16- and 32-bit sizes) is accommodated by use of an address decoder and ensuring that device addresses for cacheable devices are in a first predetermined range and any device addresses for non-cacheable devices are not in that predetermined range. Since by definition cacheable devices are 32-bit devices, pipelined operation is allowed only if the address decoder indicates the access is to a cacheable device. In that event, a next address signal is provided to the 80386. This allows the 80386 to proceed to a following cycle prior to completion of the previous cycle. For accesses which are to devices whose address indicate they are non-cacheable, a next address signal is withheld until the cycle is completed, i.e. without pipelining. The invention further provides for proper interface between a DMA mechanism (driven by a first clock) and a CPU local bus subsystem (driven by an entirely different clock). Data provided by the DMA mechanism is latched into an interface between the CPU local bus and the system bus, and a DMA cycle completed. Only after completion of the DMA cycle is detected, is the cycle on the CPU local bus allowed to complete. In this fashion, the CPU can go on to a following operation and be assured that the DMA mechanism is no longer driving the system bus.

公开(公告)号：US08819484B2

公开(公告)日：2014-08-26

申请号：US13268068

申请日：2011-10-07

申请人： Ralph M. Begun ,  Michael Decesaris ,  Randolph S. Kolvick ,  Steven L. Vanderlinden

发明人： Ralph M. Begun ,  Michael Decesaris ,  Randolph S. Kolvick ,  Steven L. Vanderlinden

IPC分类号： G06F11/00

CPC分类号： G06F11/1428 ,  G06F11/0724 ,  G06F11/0751

摘要： Methods, apparatuses, and computer program products for dynamically reconfiguring a primary processor identity within a multi-processor socket server are provided. Embodiments include detecting, by the service processor, a processor socket reconfiguration event corresponding to a first processor socket; disabling, by the service processor, the first processor socket of the server in response to detecting the processor socket reconfiguration event; and reassigning, by the service processor, the primary processor identity to a second processor socket of the server.

摘要翻译： 提供了用于在多处理器插座服务器内动态地重新配置主处理器标识的方法，装置和计算机程序产品。 实施例包括由服务处理器检测对应于第一处理器插座的处理器插座重新配置事件; 响应于检测到处理器插座重新配置事件，由服务处理器禁用服务器的第一处理器插槽; 以及由所述服务处理器将所述主处理器标识重新分配给所述服务器的第二处理器插槽。

公开(公告)号：US20130091380A1

公开(公告)日：2013-04-11

申请号：US13268068

申请日：2011-10-07

申请人： Michael Decesaris ,  Ralph M. Begun ,  Randolph S. Kolvick ,  Steven L. Vanderlinden

发明人： Michael Decesaris ,  Ralph M. Begun ,  Randolph S. Kolvick ,  Steven L. Vanderlinden

IPC分类号： G06F15/76 ,  G06F9/02 ,  G06F11/20

CPC分类号： G06F11/1428 ,  G06F11/0724 ,  G06F11/0751

摘要： Methods, apparatuses, and computer program products for dynamically reconfiguring a primary processor identity within a multi-processor socket server are provided. Embodiments include detecting, by the service processor, a processor socket reconfiguration event corresponding to a first processor socket; disabling, by the service processor, the first processor socket of the server in response to detecting the processor socket reconfiguration event; and reassigning, by the service processor, the primary processor identity to a second processor socket of the server.

摘要翻译： 提供了用于在多处理器插座服务器内动态地重新配置主处理器标识的方法，装置和计算机程序产品。 实施例包括由服务处理器检测对应于第一处理器插座的处理器插座重新配置事件; 响应于检测到处理器插座重新配置事件，由服务处理器禁用服务器的第一处理器插槽; 以及由所述服务处理器将所述主处理器标识重新分配给所述服务器的第二处理器插槽。

公开(公告)号：US20080263560A1

公开(公告)日：2008-10-23

申请号：US12165313

申请日：2008-06-30

申请人： JUSTIN P. BANDHOLZ ,  Ralph M. Begun ,  Andrew S. Heinzmann ,  Fernando A. Lopez

发明人： JUSTIN P. BANDHOLZ ,  Ralph M. Begun ,  Andrew S. Heinzmann ,  Fernando A. Lopez

IPC分类号： G06F9/50

CPC分类号： G06F21/57 ,  G06F2221/2135

摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is for securing of leased resources on a computer. The design structure includes a computer for securing resources may comprise at least one processor, a plurality of resources, wherein each resource is associated with configuration data and a programmable logic device connected to each of the plurality of resources. The programmable logic device may be configured for determining whether a resource is leased, reading un-encoded configuration data from a resource, and sending the configuration data to a first unit, if the resource is not leased. The programmable logic device may further be configured for reading encoded configuration data from a resource, decoding the configuration data, sending the configuration data that was decoded to a first unit, and logging use of the resource by the first unit, if the resource is leased.

摘要翻译： 体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构用于确保计算机上的租用资源。 设计结构包括用于保护资源的计算机可以包括至少一个处理器，多个资源，其中每个资源与配置数据相关联，以及连接到多个资源中的每一个的可编程逻辑设备。 可编程逻辑设备可以被配置为用于确定资源是否租用，从资源读取未编码的配置数据，以及如果所述资源不被租用，则将所述配置数据发送到第一单元。 可编程逻辑设备还可以被配置为：如果资源被租赁，则从资源读取编码的配置数据，解码配置数据，将被解码的配置数据发送到第一单元，以及记录第一单元的资源的使用 。