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公开(公告)号：US5555262A
公开(公告)日：1996-09-10
申请号：US522800
申请日：1995-09-01
Applicant: Ralph Urbansky
Inventor： Ralph Urbansky
CPC classification number: H04J3/0623 , H04J3/1611 , H04J2203/0003
Abstract: The invention relates to a transmission system comprising at least a transmission device for exchanging transport modules in signals of a synchronous multiplex hierarchy which signals have a frame structure of columns and rows. The transmission device (5) comprises at least an adapter circuit (5) and a switching network (5). The adapter circuit (5) is provided to delay at least a higher-order transport module up to a given position in the adapted frame structured signal. The switching network comprises at least a time stage provided to write and identify column by column the bytes to be stored of an adapted frame structured signal and to read out the bytes identified column by column in a given order to form at least an outgoing frame structured signal.
Abstract translation: 本发明涉及一种传输系统，其至少包括用于以同步多路复用层级信号交换传输模块的传输装置，这些信号具有列和行的帧结构。 传输设备（5）至少包括适配器电路（5）和交换网络（5）。 适配器电路（5）被提供用于将至少一个高阶传输模块延迟到适配帧结构信号中的给定位置。 交换网络至少包括一个时间段，用于逐列地写入和标识要存储的适配帧结构信号的字节，并且以给定的顺序逐列地读出字节，以形成至少一个输出帧结构 信号。
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公开(公告)号：US5327430A
公开(公告)日：1994-07-05
申请号：US993259
申请日：1992-12-18
Applicant: Ralph Urbansky
Inventor： Ralph Urbansky
CPC classification number: H04J3/076 , Y10S370/914
Abstract: A circuit arrangement for adapting the bit rates of two signals to each other comprises an elastic store (6). The useful data of a first frame-structured signal are written into this store (6) by means of a write address counter (7) and read out again by means of a read address counter (8). A phase comparator (16) is used for comparing the counts of these counters (7, 8). In order to largely avoid jitter in the signal that has been read, the read address counter (8) and the phase comparator (16) are incorporated in a control circuit that controls the clock for the read address counter (8). In this control circuit the output signal of the phase comparator (16) is the control error. The controlled system (17) of the control circuit consists of a controllable oscillator circuit with whose output signal and read address counter (8) is clocked. In order to avoid stationary phase shifts with a constant frequency shift, a controller (18) having a PI behavior (PI=proportionality and integration) is used.
Abstract translation: 用于使两个信号的比特率彼此适配的电路装置包括弹性存储器（6）。 通过写地址计数器（7）将第一帧结构信号的有用数据写入该存储器（6），并通过读地址计数器（8）再次读出。 相位比较器（16）用于比较这些计数器（7,8）的计数。 为了在很大程度上避免已经读出的信号中的抖动，读地址计数器（8）和相位比较器（16）被并入控制读地址计数器（8）的时钟的控制电路中。 在该控制电路中，相位比较器（16）的输出信号是控制误差。 控制电路的控制系统（17）由可控振荡器电路组成，其输出信号和读地址计数器（8）被计时。 为了避免具有恒定频移的固定相移，使用具有PI行为（PI =比例和积分）的控制器（18）。
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公开(公告)号：US5276688A
公开(公告)日：1994-01-04
申请号：US989744
申请日：1992-12-10
Applicant: Ralph Urbansky
Inventor： Ralph Urbansky
Abstract: A circuit arrangement for adjusting the bit rates of two signals of which the higher bit rate signal is structured in frames, includes a buffer memory (2), a write counter and a read counter (6, 8) as well as a phase comparator (7) and a control circuit (10). With these modules the bits of the lower bit rate signal are arranged in the frames of the higher bit rate signal. In addition to these bits negative or positive stuff bits are also inserted in the frames. In order to avoid jitter when the lower bit rate signal is recovered at the receiver end, the phase different between the two signals is determined more accurately. This effected with a counter (55, 56) whose count is applied to the phase comparator (7) to determine the digits after the decimal point for the phase difference. Furthermore, a controller (9) is provided in an automatic control system (7, 10, 8) for controlling the clock for the read counter (8), to which controller the output signal of the phase comparator (7), as well as information about the number of positive or negative bits to be stuffed during the next stuffing operation, is applied.
Abstract translation: 用于调整较高比特率信号被构造成帧的两个信号的比特率的电路装置包括缓冲存储器（2），写计数器和读计数器（6,8）以及相位比较器 7）和控制电路（10）。 利用这些模块，较低位速率信号的位被布置在较高位速率信号的帧中。 除了这些位之外，还将在帧中插入负或正填充位。 为了避免在接收端恢复较低比特率信号时的抖动，两个信号之间的相位差被更准确地确定。 这是通过计数器（55,56）实现的，其计数被施加到相位比较器（7）以确定相位差的小数点后的数字。 此外，控制器（9）设置在自动控制系统（7,10,8）中，用于控制读计数器（8）的时钟，相位比较器（7）的输出信号与控制器对应， 应用关于在下一次填充操作期间填充的正或负位的数量的信息。
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公开(公告)号：US5280502A
公开(公告)日：1994-01-18
申请号：US782710
申请日：1991-10-25
Applicant: Michael Niegel , Ralph Urbansky , Miguel Robledo
Inventor： Michael Niegel , Ralph Urbansky , Miguel Robledo
CPC classification number: H04J3/076
Abstract: The described circuit arrangement for removing stuff bits from a frame-structured signal which is available in n parallel bits, comprises a memory circuit (2) which is supplied with the parallel bits (1b). The memory circuit (2) is followed by a controllable selection circuit (3) having n outputs (3a). A control circuit (9) produces control signals (9b, 9c), which determine which bits stored in the memory circuit are transported to the n outputs (3a) of the selection circuit (3). The memory circuit (2) comprises only n delay elements by which each of the n parallel bits (1b) is delayed for the duration of one bit. So as to provide that n delay elements will be sufficient, the control circuit (9) is to block at predetermined time intervals the acceptance of new bits in one or a plurality of delay elements.
Abstract translation: 所描述的用于从每个情况下以n个并行比特发生的帧结构信号中去除填充比特的电路包含存储电路（2），并行比特（1b）被提供给该存储器电路。 具有n个输出（3a）的可控选择电路（3）连接到存储电路（2）的下游。 控制电路（9）产生控制信号（9a，9b，9c），用于确定存储在存储器电路中的哪一个位被转发到选择电路（3）的n个输出端（3a）。 存储器电路（2）仅由n个延迟分量组成，其中n个并行比特（1b）中的每一个延迟一位的持续时间。 为了确保n个延迟分量足够，控制电路（9）必须防止一个或多个延迟分量在预定时间内接受新的比特。
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公开(公告)号：US5260940A
公开(公告)日：1993-11-09
申请号：US628793
申请日：1990-12-17
Applicant: Ralph Urbansky
Inventor： Ralph Urbansky
CPC classification number: G06F5/10 , H04J3/076 , G06F2205/061
Abstract: A circuit arrangement for adapting the bit rates of two signals to each other and which comprises an elastic store (6). The useful data of a first frame-structured signal are written into this store (6) by means of a write address counter (7) and read out again by means of a read address counter (8). A phase comparator (16) is used for comparing the counts of these counters (7,8). In order to largely avoid jitter in the signal that has been read, a balancing counter (14) is provided which, on average, is stopped as often as the write address counter (7) is, but runs more smoothly than the write address counter. The means for controlling the operation of the balancing counter (14) comprise comparator circuits (12E, 12F, 12G) by means of which the operation of the frame counter (12) is monitored, an up/down counter (19) as well as various gates (11, 13, 17, 18). The phase comparator (16) compares the count of the balancing counter (14 ) to the count of the read address counter (8) and the output signal of the phase comparator (16) is used for producing the clock for the read address counter (8).
Abstract translation: 一种用于将两个信号的比特率彼此适配并且包括弹性存储器（6）的电路装置。 通过写地址计数器（7）将第一帧结构信号的有用数据写入该存储器（6），并通过读地址计数器（8）再次读出。 相位比较器（16）用于比较这些计数器（7,8）的计数。 为了大大地避免已经读取的信号中的抖动，提供平衡计数器（14），平衡计数器（14）平均被停止，如同写入地址计数器（7）那样频繁地运行，但比写入地址计数器运行更平稳 。 用于控制平衡计数器（14）的操作的装置包括比较器电路（12E，12F，12G），通过该比较器电路监视帧计数器（12）的操作，上/下计数器（19）以及 各种门（11,13,17,18）。 相位比较器（16）将平衡计数器（14）的计数与读地址计数器（8）的计数进行比较，并且相位比较器（16）的输出信号用于产生读地址计数器的时钟 8）。
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Patent Agency Ranking
公开(公告)号：US5537447A
公开(公告)日：1996-07-16
申请号：US287752
申请日：1994-08-09
Applicant: Ralph Urbansky
Inventor： Ralph Urbansky
CPC classification number: H04J3/076
Abstract: The invention relates to a transmission system comprising a synchronizer for forming a multiplex signal, comprising at least a device for conveying the multiplex signal, and a desynchronizer. The desynchronizer comprises at least a buffer store for buffering transport unit data contained in the signal, a write address generator for controlling the writing of the data in the buffer store, a control arrangement for forming a control signal for the write address generator from the signal, a read address generator for controlling the reading of the data from the buffer store, a difference circuit for forming difference values between the addresses of write and read address generators and a generating circuit for generating from the difference values a read clock signal applied to the read address generator. The control arrangement is further provided for detecting the offset of at least one transport unit in the signal and for informing a correction circuit of the detected offset, which correction circuit is used for forming the phase difference between a lower-order transport unit and a higher-order transport unit. A combiner circuit is provided for combining a correction value which is the result of the subtraction of the two phase differences and a difference value from the difference circuit.
Abstract translation: 本发明涉及一种包括用于形成多路复用信号的同步器的传输系统，包括至少一个用于传送多路复用信号的设备和一个去同步器。 所述去同步器至少包括用于缓冲信号中包含的传输单元数据的缓冲存储器，用于控制缓冲存储器中的数据写入的写地址发生器，用于根据信号形成写地址生成器的控制信号的控制装置 用于控制来自缓冲存储器的数据的读取的读地址发生器，用于在写和读地址生成器的地址之间形成差分值的差分电路和用于从差值产生施加到读取地址生成器的读时钟信号的生成电路， 读地址生成器。 该控制装置还用于检测信号中的至少一个传输单元的偏移量，并用于通知校正电路检测到的偏移，该校正电路用于形成低阶传送单元和较高传输单元之间的相位差 运输单位。 提供组合器电路，用于组合作为两个相位差的减法结果的校正值和来自差分电路的差值。
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公开(公告)号：US5361263A
公开(公告)日：1994-11-01
申请号：US148016
申请日：1993-11-05
Applicant: Ralph Urbansky
Inventor： Ralph Urbansky
CPC classification number: H04J3/07 , H04J3/0623
Abstract: A transmission system for the synchronous digital hierarchy, comprising an adaptation circuit for compensating for phase variations of an STM-N signal. The adaptation circuit (8) comprises a buffer (17, 33), a write address generator (16, 35), a read address generator (18, 44), a justification decision circuit (24, 43) and an output circuit (19, 45), for inserting justification locations for at least one container of the STM-N signal. The buffer is provided for writing and reading the container data. The write address generator is provided for generating write addresses for the data to be written and the read address generator is provided for generating read addresses for the data to be read out. The justification decision circuit is used for forming the mean value of the differences of the addresses of the read and write address generators over a specific period of time and for forming a justification signal as a function of the mean value. The output circuit is provided for generating negative or positive justification locations in the container as a function of the justification signal and for generating an output signal on the basis of the data stored in the buffer.
Abstract translation: 一种用于同步数字层级的传输系统，包括用于补偿STM-N信号的相位变化的自适应电路。 适配电路（8）包括缓冲器（17,33），写地址发生器（16,35），读地址发生器（18,44），校对判定电路（24,43）和输出电路（19） ，45），用于插入STM-N信号的至少一个容器的对齐位置。 提供缓冲区用于写入和读取容器数据。 写地址生成器被提供用于产生要写入的数据的写地址，并且提供读地址生成器用于生成要被读出的数据的读地址。 理由判定电路用于在特定时间段内形成读取和写入地址生成器的地址的差异的平均值，并且用于形成作为平均值的函数的对齐信号。 输出电路用于根据对齐信号的函数产生容器中的负调整或正调整位置，并根据存储在缓冲器中的数据产生输出信号。
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公开(公告)号：US5343476A
公开(公告)日：1994-08-30
申请号：US148017
申请日：1993-11-05
Applicant: Ralph Urbansky
Inventor： Ralph Urbansky
CPC classification number: H04J3/076 , H04J3/0623
Abstract: A digital transmission system having at least one adaptation circuit for compensating for phase variations of a STM-N signal. For inserting justification locations for at least one container of the STM-N signal, the adaptation circuit (8) includes a buffer (17, 51), a write address generator (16, 53), a read address generator (18, 61) a justification decision circuit (24, 60) and an output circuit (19, 62). The buffer stores container data in which justification locations may be inserted. The write address generator provides write addresses for data to be written in the buffer, and the read address generator provides read addresses in the buffer. In one embodiment differences between the read and write address values are combined with justification information which has been low pass filtered. In another embodiment these differences are low pass filtered and used for forming the justification decision signal. The output circuit inserts positive or negative justification locations in data read from the buffer to form the container.
Abstract translation: 一种具有用于补偿STM-N信号的相位变化的至少一个适配电路的数字传输系统。 为了插入STM-N信号的至少一个容器的对齐位置，适配电路（8）包括缓冲器（17,51），写地址发生器（16,53），读地址发生器（18,61） 理由判定电路（24,60）和输出电路（19,62）。 缓冲器存储可以插入对齐位置的容器数据。 写地址生成器为要写入缓冲器的数据提供写地址，读地址生成器在缓冲器中提供读地址。 在一个实施例中，读取和写入地址值之间的差异与被低通滤波的对齐信息组合。 在另一个实施例中，这些差异被低通滤波并用于形成对齐判定信号。 输出电路在从缓冲器读取的数据中插入正或负调整位置以形成容器。
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公开(公告)号：US5331671A
公开(公告)日：1994-07-19
申请号：US79962
申请日：1993-06-18
Applicant: Ralph Urbansky
Inventor： Ralph Urbansky
CPC classification number: H04J3/076 , H04J3/0623
Abstract: A buffer memory, in which a first signal is written and from which a second signal is read out, and a subtractor which forms the difference between the counts of a read counter and a write counter, which control reading and writing. A justification decision circuit generates a stop signal for the read counter. An accumulator accumulates the difference signal over a predetermined time interval. The accumulator output, delayed by a time interval and weighted with a second factor, and a justification signal denoting the number of stuff bits caused by the justification decision circuit between two stop instants, are added to the subtractor output in the accumulator.
Abstract translation: 缓冲存储器，其中写入第一信号并从中读出第二信号;以及减法器，其形成读取计数器和写入计数器的计数之间的差异，其控制读取和写入。 对齐判定电路产生读计数器的停止信号。 累加器在预定的时间间隔内积累差分信号。 延迟一段时间间隔并以第二因子加权的累加器输出和表示由两个停止时刻之间的调整判定电路引起的填充位数的调整信号被加到累加器中的减法器输出端。
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公开(公告)号：US5195088A
公开(公告)日：1993-03-16
申请号：US628799
申请日：1990-12-17
Applicant: Ralph Urbansky
Inventor： Ralph Urbansky
CPC classification number: H04J3/076 , Y10S370/914
Abstract: A circuit arrangement for converting the bit rate of a frame structured input signal to a predetermined nominal bit rate. The data bits of the input signal are written into an elastic store (6) at the bit rate of such signal by means of a write address counter (7), and subsequently read out again therefrom by means of a read address counter (8) at a rate within a tolerance range of the nominal bit rate. A phase comparator (16) determines the distance between the counts of such counters and produces a control error signal corresponding to such distance. In order to minimize jitter of the read out signal, the control error signal is supplied to a control circuit (18) which controls the clock produced by a clock generator (17) for the read address counter (8). The clock generator circuit includes a frequency controllable oscillator, the output of which serves as the read clock. In order to prevent stationary phase shifts from producing a constant frequency shift of the oscillator, the control circuit provides a PI behavior (proportionality and integration) of the frequency control signal supplied to the oscillator.
Abstract translation: 一种用于将帧结构输入信号的比特率转换为预定标称比特率的电路装置。 输入信号的数据位通过写入地址计数器（7）以这种信号的比特率写入弹性存储器（6）中，随后借助于读地址计数器（8）再次读出， 以标称比特率的容限范围内的速率。 相位比较器（16）确定这种计数器的计数之间的距离，并产生对应于这样的距离的控制误差信号。 为了最小化读出信号的抖动，控制误差信号被提供给控制电路（18），控制电路（18）控制由读取地址计数器（8）的时钟发生器（17）产生的时钟。 时钟发生器电路包括频率可控振荡器，其输出用作读时钟。 为了防止固定相移产生振荡器的恒定频移，控制电路提供提供给振荡器的频率控制信号的PI行为（比例和积分）。
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