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    Circuit arrangement for removing stuff bits
    2.
    发明授权
    Circuit arrangement for removing stuff bits 失效
    用于去除填充位的电路布置

    公开(公告)号：US5280502A

    公开(公告)日：1994-01-18

    申请号：US782710

    申请日：1991-10-25

    Applicant: Michael Niegel ,  Ralph Urbansky ,  Miguel Robledo

    Inventor： Michael Niegel ,  Ralph Urbansky ,  Miguel Robledo

    IPC: H04J3/07 ,  H04L7/00

    CPC classification number: H04J3/076

    Abstract: The described circuit arrangement for removing stuff bits from a frame-structured signal which is available in n parallel bits, comprises a memory circuit (2) which is supplied with the parallel bits (1b). The memory circuit (2) is followed by a controllable selection circuit (3) having n outputs (3a). A control circuit (9) produces control signals (9b, 9c), which determine which bits stored in the memory circuit are transported to the n outputs (3a) of the selection circuit (3). The memory circuit (2) comprises only n delay elements by which each of the n parallel bits (1b) is delayed for the duration of one bit. So as to provide that n delay elements will be sufficient, the control circuit (9) is to block at predetermined time intervals the acceptance of new bits in one or a plurality of delay elements.

    Abstract translation: 所描述的用于从每个情况下以n个并行比特发生的帧结构信号中去除填充比特的电路包含存储电路（2），并行比特（1b）被提供给该存储器电路。 具有n个输出（3a）的可控选择电路（3）连接到存储电路（2）的下游。 控制电路（9）产生控制信号（9a，9b，9c），用于确定存储在存储器电路中的哪一个位被转发到选择电路（3）的n个输出端（3a）。 存储器电路（2）仅由n个延迟分量组成，其中n个并行比特（1b）中的每一个延迟一位的持续时间。 为了确保n个延迟分量足够，控制电路（9）必须防止一个或多个延迟分量在预定时间内接受新的比特。

    Method and apparatus for transmitting and recieving multiplex tributary signals
    6.
    发明授权
    Method and apparatus for transmitting and recieving multiplex tributary signals 失效
    用于发送和接收多路分支信号的方法和装置

    公开(公告)号：US07254207B2

    公开(公告)日：2007-08-07

    申请号：US10166897

    申请日：2002-06-11

    Applicant: Bernd Markus K. Bleisteiner ,  Miguel Robledo ,  Konrad Sticht ,  Ralph Steffen Urbansky

    Inventor： Bernd Markus K. Bleisteiner ,  Miguel Robledo ,  Konrad Sticht ,  Ralph Steffen Urbansky

    IPC: H04L7/00

    CPC classification number: H04J3/076 ,  H04J3/0685

    Abstract: A method and apparatus are provided for transmitting and receiving a plurality of individual tributary signals in multiplex form via a common line. At the transmitting end, the tributary signals, each of which has a similar initial frequency, are converted into a compound signal having a frame structure with a common data rate. At the receiving end, each individual tributary signal is retrieved from the compound signal with its initial frequency. A phase information signal portion including a respective phase difference between each tributary signal and the compound signal is formed and inserted into the compound signal in the shape of respective coded bits. The initial frequency of each tributary signal is recovered from the phase information signal portion included in the respective coded bits belonging to the respective tributary signals.

    Abstract translation: 提供一种用于经由公共线路以多路复用形式发送和接收多个独立支路信号的方法和装置。 在发送端，每个具有类似初始频率的支路信号被转换成具有公共数据速率的帧结构的复合信号。 在接收端，从起始频率的复合信号中检索每个独立的支路信号。 形成包括各支路信号和复合信号之间的各相位差的相位信息信号部分，并以各自的编码比特的形状插入到复合信号中。 每个辅助信号的初始频率从属于相应支路信号的各个编码比特中包括的相位信息信号部分恢复。

    Digital data transmission system
    7.
    发明授权
    Digital data transmission system 失效
    数字数据传输系统

    公开(公告)号：US06920149B2

    公开(公告)日：2005-07-19

    申请号：US09865065

    申请日：2001-05-24

    Applicant: Miguel Robledo ,  Bernd Markus K. Bleisteiner ,  Martin Saeger ,  Dirk Schmidt

    Inventor： Miguel Robledo ,  Bernd Markus K. Bleisteiner ,  Martin Saeger ,  Dirk Schmidt

    IPC: H04J3/16 ,  H04Q11/04 ,  H04L12/43

    CPC classification number: H04J3/1611 ,  H04J2203/0089

    Abstract: The invention relates to a data transmission system for the frame-oriented digital data transmission of a plurality of useful signals embedded in a carrier signal, using time-division multiplex operation, rate matching being undertaken between the useful signals and the carrier signal by means of stuff locations. The data to be stuffed, and the management information for the reassignment are embedded in previously unused 8 bytes in the path layer overhead of the carrier signal superframe, and protected by an HC(6,3,3) code. Clear channel signals can advantageously be transmitted using the system, and the transmission is time-transparent and data-transparent.

    Abstract translation: 本发明涉及一种数据传输系统，用于使用时分复用操作嵌入在载波信号中的多个有用信号的面向数字数据传输的数据传输系统，利用有用信号和载波信号之间进行速率匹配，借助于 东西的位置。 待填充的数据和用于重新分配的管理信息被嵌入在载波信号超帧的路径层开销中的先前未使用的8个字节中，并被HC（6,3,3）代码保护。 可以使用系统有利地传输清除信道信号，并且传输是时间透明和数据透明的。

    Circuit arrangement for adjusting the bit rates of two signals
    8.
    发明授权
    Circuit arrangement for adjusting the bit rates of two signals 失效
    用于调整两个信号比特率的电路布置

    公开(公告)号：US5359605A

    公开(公告)日：1994-10-25

    申请号：US167432

    申请日：1993-12-13

    Applicant: Ralph Urbansky ,  Michael Niegel ,  Miguel Robledo

    Inventor： Ralph Urbansky ,  Michael Niegel ,  Miguel Robledo

    IPC: H04J3/07 ,  H04J3/06

    CPC classification number: H04J3/076

    Abstract: A circuit for adjusting the bit rates of two signals is necessary for plesiochronous multiplexers, for example, to bring the plesiochronous signals, which are to be combined to one digital signal of the next higher hierarchy, to the same bit rate. For this purpose, the circuit arrangement comprises an elastic store (4) as well as a justification decision circuit (15, 16). In order that a circuit having such features can be used for bit rates of the order of 140 Mbit/s and yet can be arranged largely in CMOS technology, the bit clocks of the first and second signals are reduced at the ratio of 1:n. Furthermore, a serial-to-parallel converter (2) converts bit groups of n serial bits of a first signal into bit groups of n parallel bits, which are written in groups into the elastic store (4) and are also read out in groups. The parallel bit groups read out are applied to a controllable selection matrix (5) having n outputs, which transmits n selected bits of more than one bit group to n outputs. The justification decision circuit (15, 16) controls the reading operation of the elastic store (4) and also the selection matrix (5).

    Abstract translation: 用于调整两个信号的比特率的电路对于同步多路复用器是必要的，例如，将要组合到下一较高层的一个数字信号的同步信号到相同的比特率。 为此，电路装置包括弹性存储器（4）以及校准判定电路（15,16）。 为了具有这样的特征的电路可以用于140Mbit / s量级的比特率，并且可以大量地在CMOS技术中被布置，第一和第二信号的比特时钟以1：n的比率被减少 。 此外，串行到并行转换器（2）将第一信号的n个串行比特的比特组转换成n个并行比特的组，它们被分组地写入到弹性存储器（4）中，并且也被分组读出 。 读出的并行比特组被应用于具有n个输出的可控选择矩阵（5），其将n个选择的多个比特组的比特发送到n个输出。 理由判定电路（15,16）控制弹性存储器（4）的读取操作以及选择矩阵（5）。

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