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公开(公告)号：US09083280B2
公开(公告)日：2015-07-14
申请号：US14452187
申请日：2014-08-05
Applicant: Rambus Inc.
Inventor： Brian Leibowitz , Hae-Chang Lee , Farshid Aryanfar , Kun-Yung Chang , Jie Shen
CPC classification number: H03D13/00 , H03L7/08 , H03L7/0814 , H03L7/0816 , H03L7/085
Abstract: A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.
Abstract translation: 相位检测电路可以包括两个相位检测器，每个相位检测器响应于相位对齐的输入信号而产生非零输出。 输入信号基于两个周期信号。 相位检测电路从另一相位检测器的输出信号中减去一相位检测器的输出信号，当周期信号同相时产生具有零值的信号。 或者，相位检测器产生指示周期信号之间的相位差的相位比较信号。 相位比较信号响应于相位检测器的相位输入信号具有非零值。 输入信号基于周期信号。 输出电路接收相位比较信号，并响应于同相对齐的周期信号产生具有零值的输出。
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公开(公告)号：US20150049798A1
公开(公告)日：2015-02-19
申请号：US14363054
申请日：2012-11-30
Applicant: RAMBUS INC.
Inventor： Masum Hossein , Farshid Aryanfar , Jihong Ren , Jared L. Zerbe
CPC classification number: G06F1/3203 , H04B1/12 , H04L7/0054 , H04L7/033 , H04L25/03006 , H04L25/03012 , H04L25/03057 , H04L25/03127 , H04L25/03146 , H04L25/03853 , H04L2025/03433
Abstract: A receiver integrated circuit is disclosed that includes a filter and a linear equalization circuit. The filter has an input to receive a signal symbols a main tap and a pre-cursor tap to reduces a pre-cursor ISI acting on the data symbols. The linear equalization circuit couples to the output and cooperates with the filter to further reduce ISI.
Abstract translation: 公开了一种接收机集成电路，其包括滤波器和线性均衡电路。 滤波器具有用于接收主要抽头和前置光标抽头的信号符号的输入，以减少作用在数据符号上的前标ISI。 线性均衡电路耦合到输出并与滤波器配合以进一步减少ISI。
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公开(公告)号：US20140333356A1
公开(公告)日：2014-11-13
申请号：US14089094
申请日：2013-11-25
Applicant: Rambus Inc.
Inventor： Farshid Aryanfar , Hae-Chang Lee , Kun-Yung Chang , Ting Wu , Carl Werner , Masoud Koochakzadeh
CPC classification number: H03L7/093 , G06F1/10 , H03L7/0802
Abstract: A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.
Abstract translation: 信号分配网络具有每个段具有缓冲电路，耦合到缓冲电路的传输线，通过传输线耦合到缓冲电路的电感器，以及耦合到电感器的可变电容电路，并通过 传输线。 可变电容电路的电容被设定为确定通过传输线传输的信号的相位和幅度。 信号分配网络可以包括相位检测器，环路滤波器电路和谐振延迟电路。 相位检测器将第一周期信号的相位与第二周期信号的相位进行比较。 谐振延迟电路具有可变阻抗电路，其具有基于环路滤波器电路的输出信号的变化而变化的阻抗。
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公开(公告)号：US20140323054A1
公开(公告)日：2014-10-30
申请号：US14364002
申请日：2012-12-20
Applicant: RAMBUS INC.
Inventor： Farshid Aryanfar , Carl W. Werner , Aykut Bultan
IPC: H04B7/005
CPC classification number: H04B7/005 , H04L25/0204
Abstract: The disclosed embodiments relate to a system that performs channel-sounding operations in a multi-antenna wireless communication system. During operation, the system first performs channel-sounding operations between a first client and a second client in a first frequency band. These channel-sounding operations involve transmitting a series of known tones between the first client and the second client and using signals received as a result of the transmissions to finds a strongest path between the first client and the second client. Next, the system uses the identified strongest path to improve channel-sounding operations in a second frequency band.
Abstract translation: 所公开的实施例涉及在多天线无线通信系统中执行信道探测操作的系统。 在操作期间，系统首先在第一频带中在第一客户端和第二客户端之间执行信道探测操作。 这些信道探测操作涉及在第一客户机和第二客户端之间传送一系列已知的音调，并使用作为传输结果而接收的信号，以在第一客户机和第二客户机之间找到最强的路径。 接下来，系统使用所识别的最强路径来改善第二频带中的频道探测操作。
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公开(公告)号：US10587276B2
公开(公告)日：2020-03-10
申请号：US16382580
申请日：2019-04-12
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar
Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.
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Patent Agency Ranking
公开(公告)号：US10389303B2
公开(公告)日：2019-08-20
申请号：US15921480
申请日：2018-03-14
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
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公开(公告)号：US20190253059A1
公开(公告)日：2019-08-15
申请号：US16382580
申请日：2019-04-12
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar
CPC classification number: H03L7/235 , H03L7/0805 , H03L7/081 , H03L7/099 , H03L7/0995 , H03L7/18 , H03L7/23
Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.
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公开(公告)号：US10298244B2
公开(公告)日：2019-05-21
申请号：US15605932
申请日：2017-05-25
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar
Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.
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公开(公告)号：US20180278210A1
公开(公告)日：2018-09-27
申请号：US15921480
申请日：2018-03-14
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
CPC classification number: H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099 , H05K999/99
Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
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公开(公告)号：US09692431B2
公开(公告)日：2017-06-27
申请号：US14746618
申请日：2015-06-22
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar
CPC classification number: H03L7/235 , H03L7/0805 , H03L7/081 , H03L7/099 , H03L7/0995 , H03L7/18 , H03L7/23
Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.
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