公开(公告)号：US20210157582A1

公开(公告)日：2021-05-27

申请号：US17093227

申请日：2020-11-09

Applicant: Rambus Inc.

Inventor： Amogh AGRAWAL ,  Thomas VOGELSANG ,  Steven C. WOO

IPC: G06F9/30 ,  G06F9/38 ,  H01L21/768

Abstract: An array of processing elements are arranged in a three-dimensional array. Each of the processing elements includes or is coupled to a dedicated memory. The processing elements of the array are intercoupled to their nearest neighbor processing elements. A processing element on a first die may be intercoupled to a first processing element on a second die that is located directly above the processing element, a second processing element on a third die that is located directly below the processing element, and the four adjacent processing elements on the first die. This intercoupling allows data to flow from processing element to processing element in the three directions. These dataflows are reconfigurable so that they may be optimized for the task. The data flows of the array may be configured into one or more loops that periodically recycle data in order to accomplish different parts of a calculation.