公开(公告)号：US20240176497A1

公开(公告)日：2024-05-30

申请号：US18519359

申请日：2023-11-27

Applicant: Rambus Inc.

Inventor： Liji GOPALAKRISHNAN ,  Thomas VOGELSANG ,  John Eric LINSTADT

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40622 ,  G06F13/1636

Abstract: ABSTRACT OF DISCLOSURE A memory controller combines information about which memory component segments are not being refreshed with the information about which rows are going to be refreshed next, to determine, for the current refresh command, the total number of rows that are going to be refreshed. Based on this total number of rows, the memory controller selects how long to wait after the refresh command before issuing a next subsequent command. When the combination of masked segments and the refresh scheme results in less than the ‘nominal’ number of rows typically refreshed in response to a single refresh command, the waiting period before the next command (e.g., non-refresh command) is issued may be reduced from the ‘nominal’ minimum time period, thereby allowing the next command to be issued earlier.

公开(公告)号：US20240146546A1

公开(公告)日：2024-05-02

申请号：US18278374

申请日：2022-02-25

Applicant: Rambus Inc.

Inventor： Scott C. BEST ,  Thomas VOGELSANG ,  Michael Alexander HAMBURG ,  Mark Evan MARSON ,  Helena HANDSCHUH ,  HAMPEL E. Craig ,  Kenneth Lee WRIGHT

IPC: H04L9/32 ,  G06F21/73

CPC classification number: H04L9/3268 ,  G06F21/73

Abstract: An asymmetric key cryptographic system is used to generate a cryptographic certificate for authenticating a memory module. This certificate is generated based on information, readable by the authenticator (e.g., host system), from at least one device on the memory module that is not read in order to obtain the certificate. For example, the certificate for authenticating a module may be stored in the nonvolatile memory of a serial presence detect device. The certificate itself, however, is based at least in part on information read from at least one other device on the memory module. Examples of this other device include a registering clock driver, DRAM device(s), and/or data buffer device(s). In an embodiment, the information read from a device (e.g., DRAM) may be based on one or more device fingerprint(s) derived from physical variations that occur naturally, and inevitably, during integrated circuit manufacturing.

公开(公告)号：US20170214869A1

公开(公告)日：2017-07-27

申请号：US15328207

申请日：2015-07-23

Applicant: Rambus Inc.

Inventor： John LADD ,  Michael GUIDASH ,  Craig M. SMITH ,  Thomas VOGELSANG ,  Jay ENDSLEY ,  Michael T. CHING ,  James E. HARRIS

IPC: H04N5/357 ,  H04N5/369 ,  H04N5/378 ,  H04N5/365

CPC classification number: H04N5/3655 ,  H04N5/355 ,  H04N5/357 ,  H04N5/3575 ,  H04N5/3651 ,  H04N5/3698 ,  H04N5/3745 ,  H04N5/37455 ,  H04N5/378

Abstract: A sequence of control voltage levels are applied to a control signal line capacitively coupled to a floating diffusion node of a pixel to sequentially adjust a voltage level of the floating diffusion node. A pixel output signal representative of the voltage level of the floating diffusion node is compared with a reference voltage to identify a first control voltage level of the sequence of control voltage levels for which the voltage level of the floating diffusion node exceeds the reference voltage.

公开(公告)号：US20240127882A1

公开(公告)日：2024-04-18

申请号：US18497149

申请日：2023-10-30

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  John Eric Linstadt ,  Liji Gopalakrishnan

IPC: G11C11/408 ,  G06F13/42 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4085 ,  G06F13/4282 ,  G11C11/4091 ,  G11C11/4094

Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.

公开(公告)号：US20230125262A1

公开(公告)日：2023-04-27

申请号：US17963065

申请日：2022-10-10

Applicant: Rambus Inc.

Inventor： Mark D. KELLAM ,  Dongyun LEE ,  Thomas VOGELSANG ,  Steven C. WOO

IPC: G02B6/293 ,  G02B6/12 ,  H04B10/50

Abstract: Command/address and timing information is distributed to buffer integrated circuits on a module using multiple wavelengths of light modulated with the same information. Each individual wavelength of modulated light carrying command/address information is received by a corresponding single buffer device that deserializes the command/address information and communicates it electrically to memory devices(s). Likewise, each individual wavelength of modulated light carrying timing/synchronization/clock information is received by a corresponding single buffer device and used to synchronize accesses to the memory device(s). Thus, multiple buffer integrated circuits on a module each receive information from the CPU using different wavelengths of light transmitted on the same waveguide.

公开(公告)号：US20220147468A1

公开(公告)日：2022-05-12

申请号：US17438844

申请日：2020-03-19

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  Craig E. HAMPEL

IPC: G06F13/16 ,  G06F7/483

Abstract: Space in a memory is allocated based on the highest used precision. When the maximum used precision is not being used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and the memory while the rest are not. A given floating point number is distributed over non-contiguous addresses. Each portion of the given floating point number is located at the same offset within the access units, groups, and/or memory arrays. This allows a sequencer in the memory device to successively access a precision dependent number of access units, groups, and/or memory arrays without receiving additional requests over the memory channel.

公开(公告)号：US20210157582A1

公开(公告)日：2021-05-27

申请号：US17093227

申请日：2020-11-09

Applicant: Rambus Inc.

Inventor： Amogh AGRAWAL ,  Thomas VOGELSANG ,  Steven C. WOO

IPC: G06F9/30 ,  G06F9/38 ,  H01L21/768

Abstract: An array of processing elements are arranged in a three-dimensional array. Each of the processing elements includes or is coupled to a dedicated memory. The processing elements of the array are intercoupled to their nearest neighbor processing elements. A processing element on a first die may be intercoupled to a first processing element on a second die that is located directly above the processing element, a second processing element on a third die that is located directly below the processing element, and the four adjacent processing elements on the first die. This intercoupling allows data to flow from processing element to processing element in the three directions. These dataflows are reconfigurable so that they may be optimized for the task. The data flows of the array may be configured into one or more loops that periodically recycle data in order to accomplish different parts of a calculation.

公开(公告)号：US20240241670A1

公开(公告)日：2024-07-18

申请号：US18427191

申请日：2024-01-30

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  Michael Raymond MILLER ,  Steven C. WOO

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F3/0659 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0673 ,  G11C7/1006

Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die has a base logic die and one or more custom logic or processor die. The processor logic die snoops commands sent to and through the stack. In particular, the processor logic die may snoop mode setting commands (e.g., mode register set—MRS commands). At least one mode setting command that is ignored by the DRAM in the stack is used to communicate a command to the processor logic die. In response the processor logic die may prevent commands, addresses, and data from reaching the DRAM die(s). This enables the processor logic die to send commands/addresses and communicate data with the DRAM die(s). While being able to send commands/addresses and communicate data with the DRAM die(s), the processor logic die may execute software using the DRAM die(s) for program and/or data storage and retrieval.

公开(公告)号：US20230395118A1

公开(公告)日：2023-12-07

申请号：US18206241

申请日：2023-06-06

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  Torsten PARTSCH

IPC: G11C11/406 ,  G11C11/4078

CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4078

Abstract: A 3D DRAM architecture may have one or more layers of cells where the access transistors of the memory cell array are fabricated among the metal layers rather than in the semiconductor (e.g., silicon) substrate. Counter and counter control circuits for each row in the memory cell array are fabricated under the array. These counters track the number of row hammers each row experiences. When a counter indicates a row has experienced a threshold number of row hammers, that row is refreshed. The row may be refreshed immediately after the current row is closed. The row may be scheduled to be refreshed as part of a regular refresh sequence. A signal may be sent to the memory controlling indicating that the bank with the row being refreshed immediately should not be accessed until the refresh is complete.

公开(公告)号：US20220328078A1

公开(公告)日：2022-10-13

申请号：US17634370

申请日：2020-08-13

Applicant: Rambus Inc.

Inventor： John Eric LINSTADT ,  Liji GOPALAKRISHNAN ,  Thomas VOGELSANG

IPC: G11C7/10 ,  G11C7/22

Abstract: The memory banks of a memory device are arranged and operated in groups and the groups are further arranged and operated as clusters of these groups. Successive accesses to banks that are within different bank group clusters may be issued at a first time interval. Successive accesses to banks that are within different bank groups within the same cluster can be issued no faster than a second time interval. And, successive accesses to banks that are within the same bank group may be issued no faster than a third time interval. The memory banks of a memory device may have multiple rows open at the same time. The rows that can be open at the same time is determined by the rows that are already open. These memory banks are also arranged and operated in groups that have three different minimum time intervals.