公开(公告)号：US20240146546A1

公开(公告)日：2024-05-02

申请号：US18278374

申请日：2022-02-25

Applicant: Rambus Inc.

Inventor： Scott C. BEST ,  Thomas VOGELSANG ,  Michael Alexander HAMBURG ,  Mark Evan MARSON ,  Helena HANDSCHUH ,  HAMPEL E. Craig ,  Kenneth Lee WRIGHT

IPC: H04L9/32 ,  G06F21/73

CPC classification number: H04L9/3268 ,  G06F21/73

Abstract: An asymmetric key cryptographic system is used to generate a cryptographic certificate for authenticating a memory module. This certificate is generated based on information, readable by the authenticator (e.g., host system), from at least one device on the memory module that is not read in order to obtain the certificate. For example, the certificate for authenticating a module may be stored in the nonvolatile memory of a serial presence detect device. The certificate itself, however, is based at least in part on information read from at least one other device on the memory module. Examples of this other device include a registering clock driver, DRAM device(s), and/or data buffer device(s). In an embodiment, the information read from a device (e.g., DRAM) may be based on one or more device fingerprint(s) derived from physical variations that occur naturally, and inevitably, during integrated circuit manufacturing.

公开(公告)号：US20230260564A1

公开(公告)日：2023-08-17

申请号：US18104069

申请日：2023-01-31

Applicant: Rambus Inc.

Inventor： Torsten PARTSCH ,  John Eric LINSTADT ,  Helena HANDSCHUH

IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/408

CPC classification number: G11C11/40626 ,  G11C11/4091 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4085

Abstract: A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not refreshed will, after a time, lose their contents thereby reducing the time interval for attack. An external signal can cause the isolation of a memory device or module and initiation of automatic erasure of the memory contents of the device or module using one of the methods disclosed herein. The trigger for the external signal may be one or more of temperature changes/conditions, loss of power, and/or external commands from a controller.

公开(公告)号：US20210375354A1

公开(公告)日：2021-12-02

申请号：US17325977

申请日：2021-05-20

Applicant: Rambus Inc.

Inventor： Torsten PARTSCH ,  John Eric LINSTADT ,  Helena HANDSCHUH

IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4076

Abstract: A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not refreshed will, after a time, lose their contents thereby reducing the time interval for attack. An external signal can cause the isolation of a memory device or module and initiation of automatic erasure of the memory contents of the device or module using one of the methods disclosed herein. The trigger for the external signal may be one or more of temperature changes/conditions, loss of power, and/or external commands from a controller.

公开(公告)号：US20240212739A1

公开(公告)日：2024-06-27

申请号：US18403569

申请日：2024-01-03

Applicant: Rambus Inc.

Inventor： Torsten PARTSCH ,  John Eric LINSTADT ,  Helena HANDSCHUH

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/40626 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094

Abstract: A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not refreshed will, after a time, lose their contents thereby reducing the time interval for attack. An external signal can cause the isolation of a memory device or module and initiation of automatic erasure of the memory contents of the device or module using one of the methods disclosed herein. The trigger for the external signal may be one or more of temperature changes/conditions, loss of power, and/or external commands from a controller.