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公开(公告)号：US20230297474A1
公开(公告)日：2023-09-21
申请号：US18130810
申请日：2023-04-04
Applicant: Rambus Inc.
Inventor： Michael Raymond MILLER , Stephen MAGEE , John Eric LINSTADT
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/0673 , G06F3/0644 , G06F3/0625 , G06F11/1048
Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.
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公开(公告)号：US20210241844A1
公开(公告)日：2021-08-05
申请号：US17049282
申请日：2019-03-20
Applicant: Rambus Inc.
Inventor： John Eric LINSTADT , Frederick A. WARE
Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.
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公开(公告)号：US20200349005A1
公开(公告)日：2020-11-05
申请号：US16881859
申请日：2020-05-22
Applicant: Rambus Inc.
Inventor： Michael MILLER , Stephen MAGEE , John Eric LINSTADT
Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.
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公开(公告)号：US20200012429A1
公开(公告)日：2020-01-09
申请号：US16518198
申请日：2019-07-22
Applicant: Rambus Inc.
Inventor： Frederick A. WARE , John Eric LINSTADT
IPC: G06F3/06 , G11C7/06 , G11C11/4091 , G11C11/4076 , G11C7/22 , G11C7/18 , G11C11/4097
Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.
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公开(公告)号：US20240370331A1
公开(公告)日：2024-11-07
申请号：US18649009
申请日：2024-04-29
Applicant: Rambus Inc.
Inventor： Taeksang SONG , John Eric LINSTADT , Steven C. WOO , Craig E. HAMPEL , Brent Steven HAUKNESS , Christopher HAYWOOD
IPC: G06F11/10
Abstract: A random access memory device includes memory cells in each row for storing metadata related to accesses to that row. These metadata dedicated memory cells may store counter values that may be updated (e.g., incremented or decremented) when certain events occur (e.g., activate row—ACT, column read—CAS, error detected, etc.). Which events cause an update of the metadata stored in a row, and under what conditions related to the metadata/count value (e.g., threshold, match, threshold value, etc.) cause further action to be taken (e.g., alert controller, set mode register, etc.) are configurable by a controller. Additional functions related to the metadata/counters are also configurable such as scanning counter values to determine the row address with highest or lowest value and pattern matching (e.g., process identification match/mismatch).
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Patent Agency Ranking
公开(公告)号：US20240176497A1
公开(公告)日：2024-05-30
申请号：US18519359
申请日：2023-11-27
Applicant: Rambus Inc.
Inventor： Liji GOPALAKRISHNAN , Thomas VOGELSANG , John Eric LINSTADT
IPC: G06F3/06 , G11C11/406
CPC classification number: G06F3/0613 , G06F3/0659 , G06F3/0673 , G11C11/40622 , G06F13/1636
Abstract: ABSTRACT OF DISCLOSURE A memory controller combines information about which memory component segments are not being refreshed with the information about which rows are going to be refreshed next, to determine, for the current refresh command, the total number of rows that are going to be refreshed. Based on this total number of rows, the memory controller selects how long to wait after the refresh command before issuing a next subsequent command. When the combination of masked segments and the refresh scheme results in less than the ‘nominal’ number of rows typically refreshed in response to a single refresh command, the waiting period before the next command (e.g., non-refresh command) is issued may be reduced from the ‘nominal’ minimum time period, thereby allowing the next command to be issued earlier.
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公开(公告)号：US20240012710A1
公开(公告)日：2024-01-11
申请号：US18213828
申请日：2023-06-24
Applicant: Rambus Inc.
Inventor： Evan Lawrence ERICKSON , John Eric LINSTADT
IPC: G06F11/10
CPC classification number: G06F11/10
Abstract: When writing a block (e.g., cache line) of data to a memory, error detection and correction (EDC) information (check) symbols are calculated. The block of data, a first portion of the check symbols, and metadata are all written concurrently at a first address. The remaining portion of the check symbols are written at a second, different from the first, address. When reading the block of data, a first read command accesses the block of data, the first portion of the check symbols, and the metadata from the first address. Only the first portion of the check symbols is used to determine a first number of errors (if any) in the accessed data. If the first number of errors meets a threshold number of errors, a second read command is issued to access the second portion of the check symbols.
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公开(公告)号：US20230305915A1
公开(公告)日：2023-09-28
申请号：US18092556
申请日：2023-01-03
Applicant: Rambus Inc.
Inventor： Thomas J. GIOVANNINI , Catherine CHEN , Scott C. BEST , John Eric LINSTADT , Frederick A. WARE
CPC classification number: G06F11/079 , G06F11/073 , G06F11/0772 , G06F13/00 , G11C5/04 , G11C7/20 , G11C8/12 , G11C29/26 , G11C29/44
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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公开(公告)号：US20220327021A1
公开(公告)日：2022-10-13
申请号：US17734464
申请日：2022-05-02
Applicant: Rambus Inc.
Inventor： Michael Raymond MILLER , Stephen MAGEE , John Eric LINSTADT
Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.
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公开(公告)号：US20240355407A1
公开(公告)日：2024-10-24
申请号：US18648969
申请日：2024-04-29
Applicant: Rambus Inc.
Inventor： John Eric LINSTADT , Frederick A. Ware
Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.
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