公开(公告)号：US10705989B2

公开(公告)日：2020-07-07

申请号：US15864732

申请日：2018-01-08

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Holden Jessup

IPC: G06F13/16

Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.

公开(公告)号：US20180181505A1

公开(公告)日：2018-06-28

申请号：US15864732

申请日：2018-01-08

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Holden Jessup

IPC: G06F13/16

Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.

公开(公告)号：US20250156350A1

公开(公告)日：2025-05-15

申请号：US18920424

申请日：2024-10-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Holden Jessup

IPC: G06F13/16

Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.

公开(公告)号：US20230409499A1

公开(公告)日：2023-12-21

申请号：US18138667

申请日：2023-04-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Holden Jessup

IPC: G06F13/16

CPC classification number: G06F13/1689

Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.

公开(公告)号：US20210011866A1

公开(公告)日：2021-01-14

申请号：US16914213

申请日：2020-06-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Holden Jessup

IPC: G06F13/16

Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.

公开(公告)号：US12130759B2

公开(公告)日：2024-10-29

申请号：US18138667

申请日：2023-04-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Holden Jessup

IPC: G06F13/16

CPC classification number: G06F13/1689

Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.

公开(公告)号：US11645214B2

公开(公告)日：2023-05-09

申请号：US16914213

申请日：2020-06-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Holden Jessup

IPC: G06F12/00 ,  G06F13/16

CPC classification number: G06F13/1689

Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.