公开(公告)号：US09747230B2

公开(公告)日：2017-08-29

申请号：US14408955

申请日：2013-10-14

Applicant: Rambus Inc.

Inventor： Minghui Han ,  Amir Amirkhany ,  Ravindranath Kollipara ,  Ralf Michael Schmitt

IPC: G06F13/36 ,  G06F13/28 ,  G06F3/06 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10

CPC classification number: G06F13/28 ,  G06F3/0611 ,  G06F3/0635 ,  G06F3/0683 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1084

Abstract: A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.