公开(公告)号：US09231731B1

公开(公告)日：2016-01-05

申请号：US13857329

申请日：2013-04-05

Applicant: Rambus Inc.

Inventor： Huy M. Nguyen ,  Kambiz Kaviani ,  Reza Navid ,  Jason Chia-Jen Wei ,  Xudong Shi ,  Scott C. Best

IPC: H03K19/094 ,  H04L1/00

CPC classification number: H04L1/0036 ,  H04L25/0276 ,  H04L25/0278

Abstract: The common-mode input voltage of a common-gate input amplifier receiving a differential signal is set in an open-loop manner by basing the bias current and/or source load impedances of the common-gate amplifier on a transmitter bias current and driving impedance. The common-mode input voltage of a common-gate input amplifier receiving a differential signal may be set in a closed-loop manner using a feedback loop having a captured target voltage compared to the common-mode input voltage at a node of the amplifier. The common-mode input voltage of a common-gate input amplifier receiving a differential signal may be set in a continuous time closed loop manner by sending a reference current through resistances that are multiples of a resistance used to generate the reference current.

Abstract translation: 接收差分信号的公共栅极输入放大器的共模输入电压通过基于发射极偏置电流和驱动阻抗的公共栅极放大器的偏置电流和/或源极负载阻抗，以开环方式设置 。 接收差分信号的公共栅极输入放大器的共模输入电压可以使用具有与放大器的节点处的共模输入电压相比的捕获的目标电压的反馈环路以闭环方式设置。 接收差分信号的公共栅极输入放大器的共模输入电压可以通过以参考电流的形式发送参考电流而设置为连续时间闭环方式，电阻是用于产生参考电流的电阻的倍数。

公开(公告)号：US08933729B1

公开(公告)日：2015-01-13

申请号：US13834970

申请日：2013-03-15

Applicant: Rambus Inc.

Inventor： Xudong Shi ,  Reza Navid ,  Jason Chia-Jen Wei ,  Huy M. Nguyen ,  Kambiz Kaviani

IPC: H03B1/00 ,  H03K3/00 ,  H03F3/45 ,  H03K5/00

CPC classification number: H03K5/00 ,  H03F3/195 ,  H03F3/45179 ,  H03F3/45654 ,  H03F3/68 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45498 ,  H03F2203/45702 ,  H04L25/0276

Abstract: Differential receivers are “stacked” and independently calibrated to different common-mode voltages. The different common-mode voltages may correspond to the common-mode voltages of stacked transmission circuits. Multiple stacks of samplers are connected to the same channels. The clocking of each stack of sampler circuits is phased (timed) such that the samplers in a given stack are not resolving at the same time. Samplers in a different stack and receiving a different common-mode voltage resolve at the same time.

Abstract translation: 差分接收器“堆叠”，并独立校准到不同的共模电压。 不同的共模电压可以对应于堆叠的发送电路的共模电压。 多个采样器堆叠连接到相同的通道。 每个采样器电路堆的时钟被定时（定时），使得给定堆栈中的采样器不能同时解析。 在不同的堆叠中并且接收不同共模电压的采样器同时解析。