公开(公告)号：US6121827A

公开(公告)日：2000-09-19

申请号：US293510

申请日：1999-04-15

申请人： Ramin Khoini-Poorfard ,  Lysander B. Lim

发明人： Ramin Khoini-Poorfard ,  Lysander B. Lim

IPC分类号： H01L23/50 ,  H01L25/00

CPC分类号： H01L23/50 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6688 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/3025

摘要： A mixed signal integrated circuit board having decreased sensitivity of analog circuitry to digital circuitry noise is disclosed. In the mixed-signal integrated board of the present invention, a new (second) analog ground is created. This new analog ground is not limited by the manufacturing specification of connectivity to the substrate of the circuit board and is thereby free of transient noise generated by digital components on the board. In a mixed-signal integrated circuit board of the present invention, the new analog ground becomes the preferred ground and is utilized in many sensitive analog applications including voltage and current measurements. The new analog ground is easy to create as it does not involved complicated circuitry. The new analog ground may be created even after the initial circuit schematics has been created.

摘要翻译： 公开了一种具有降低的模拟电路对数字电路噪声灵敏度的混合信号集成电路板。 在本发明的混合信号集成电路板中，产生新的（第二）模拟地。 这种新的模拟接地不受电路板基板的连接的制造规范的限制，从而不受板上数字部件产生的瞬态噪声的影响。 在本发明的混合信号集成电路板中，新的模拟地被成为优选的地面，并被用于包括电压和电流测量在内的许多敏感的模拟应用中。 新的模拟地线容易创建，因为它不涉及复杂的电路。 即使在创建初始电路原理图之后，也可能会创建新的模拟地。

公开(公告)号：US06603804B1

公开(公告)日：2003-08-05

申请号：US09411152

申请日：1999-10-01

申请人： Ramin Khoini-Poorfard ,  Lysander B. Lim ,  Malcolm H. Smith

发明人： Ramin Khoini-Poorfard ,  Lysander B. Lim ,  Malcolm H. Smith

IPC分类号： H04B169

CPC分类号： H03H17/0223

摘要： A transmit portion of a WB-CDMA transceiver generates one or more spread data streams having values represented by a single bit, allowing for filtering of spread and combined data streams with a root raised cosine (RRC) filter employing single-bit multipliers. The RRC filter is a digital filter that i) employs multiplication of two values in which the length of at least one value is one bit; ii) is preferably implemented with muxs or a simple logic operator; and iii) may employ upsampling and modulation encoding of filter coefficients to reduce the coefficient length to, for example, one bit. The RRC filter may be an FIR filter having either one-bit or multi-bit coefficients, and apply RRC filtering to a spread user stream either before or after the spread user streams are combined. For some implementations, RRC filters are employed to filter each spread user stream prior to combining several processed user steams. For other implementations, the multi-bit valued data stream representing the combined user streams is upsampled to form an upsampled data stream of single-bit values, and RRC filtering is then applied to the upsampled data stream. Alternatively, implementations may use upsampled RRC filter coefficients that allow RRC filtering on the combined spread user streams represented as a sequence of multi-bit values.

摘要翻译： WB-CDMA收发器的发送部分产生具有由单个比特表示的值的一个或多个扩展数据流，允许使用单比特乘法器的根升余弦（RRC）滤波器对扩展和组合数据流进行滤波。 RRC滤波器是数字滤波器，其i）采用其中至少一个值的长度为1比特的两个值的乘法; ii）优选地用多路复用器或简单的逻辑运算符实现; 和iii）可以采用滤波器系数的上采样和调制编码来将系数长度减小到例如一位。 RRC滤波器可以是具有一比特或多比特系数的FIR滤波器，并且在扩展用户流合并之前或之后对扩展用户流应用RRC滤波。 对于一些实现方式，采用RRC滤波器来在组合若干已处理的用户流之前过滤每个扩展用户流。 对于其他实施方式，表示组合用户流的多位值数据流被上采样以形成单位值的上采样数据流，然后将RRC滤波应用于上采样数据流。 或者，实现可以使用上采样的RRC滤波器系数，其允许对表示为多位值序列的组合扩展用户流进行RRC过滤。

公开(公告)号：US06369622B1

公开(公告)日：2002-04-09

申请号：US09408770

申请日：1999-09-29

申请人： Lysander B. Lim ,  Malcolm Harold Smith ,  H. Scott Fetterman

发明人： Lysander B. Lim ,  Malcolm Harold Smith ,  H. Scott Fetterman

IPC分类号： H03B1900

CPC分类号： H03B19/14

摘要： A phase shifter network receives at an input node an input clock signal which does not contain higher order harmonics and generates first and second phase-shifted clock signals which are 90° apart and which have the same frequency as the input clock signal. First and second voltage comparators receive the first and second phase-shifted clock signals, respectively, and generates first and second squared clock signals, respectively, which are 90° apart and which have the same frequency as the input clock signal. A combiner combines the first and second squared clock signals to produce an output clock signal having twice the frequency of the input clock signal.

摘要翻译： 移相器网络在输入节点处接收不包含较高次谐波的输入时钟信号，并产生与输入时钟信号相同且相差90°并且具有相同频率的第一和第二相移时钟信号。 第一和第二电压比较器分别接收第一和第二相移时钟信号，分别产生与输入时钟信号相同的90°的第一和第二平方时钟信号。 组合器组合第一和第二平方时钟信号以产生具有输入时钟信号频率的两倍的输出时钟信号。