公开(公告)号：US20120155529A1

公开(公告)日：2012-06-21

申请号：US12973242

申请日：2010-12-20

申请人： Ramon Mangaser ,  Shefali Walia ,  Edoardo Prete ,  Jonathan P. Dowling ,  Gerald R. Talbot ,  Sharad N. Vittal

发明人： Ramon Mangaser ,  Shefali Walia ,  Edoardo Prete ,  Jonathan P. Dowling ,  Gerald R. Talbot ,  Sharad N. Vittal

IPC分类号： H03K5/159

CPC分类号： H04L25/03878 ,  H04L25/03057

摘要： A decision feedback equalization (DFE) receiver and method are provided. The DFE receiver is configured to sample data bits from a data bus. The DFE receiver includes a data sampler configured to sample a current data bit from the data bus using one of a first, second and third voltage reference. The DFE receiver also includes multiplexing logic configured to select one of the first, second and third voltage references based on a prior data bus level. The wherein the first voltage reference is selected if the prior data bus level was a logic zero. The second voltage reference is selected if the prior data bus level was a logic one. The third voltage reference is selected if the prior data bus level was tri-state.

摘要翻译： 提供了一种判决反馈均衡（DFE）接收机和方法。 DFE接收器配置为从数据总线采样数据位。 DFE接收器包括数据采样器，其被配置为使用第一，第二和第三参考电压之一从数据总线采样当前数据位。 DFE接收机还包括被配置为基于先前的数据总线电平来选择第一，第二和第三电压基准之一的多路复用逻辑。 其中如果先前数据总线电平为逻辑0，则选择第一参考电压。 如果先前的数据总线电平为逻辑1，则选择第二个参考电压。 如果先前的数据总线电平为三态，则选择第三个参考电压。

公开(公告)号：US08553754B2

公开(公告)日：2013-10-08

申请号：US12973242

申请日：2010-12-20

申请人： Ramon Mangaser ,  Shefali Walia ,  Edoardo Prete ,  Jonathan P. Dowling ,  Gerald R. Talbot ,  Sharad N. Vittal

发明人： Ramon Mangaser ,  Shefali Walia ,  Edoardo Prete ,  Jonathan P. Dowling ,  Gerald R. Talbot ,  Sharad N. Vittal

IPC分类号： H03K5/159 ,  H03H7/30 ,  H03H7/40

CPC分类号： H04L25/03878 ,  H04L25/03057

摘要： A decision feedback equalization (DFE) receiver and method are provided. The DFE receiver is configured to sample data bits from a data bus. The DFE receiver includes a data sampler configured to sample a current data bit from the data bus using one of a first, second and third voltage reference. The DFE receiver also includes multiplexing logic configured to select one of the first, second and third voltage references based on a prior data bus level. The wherein the first voltage reference is selected if the prior data bus level was a logic zero. The second voltage reference is selected if the prior data bus level was a logic one. The third voltage reference is selected if the prior data bus level was tri-state.

摘要翻译： 提供了一种判决反馈均衡（DFE）接收机和方法。 DFE接收器配置为从数据总线采样数据位。 DFE接收器包括数据采样器，其被配置为使用第一，第二和第三参考电压之一从数据总线采样当前数据位。 DFE接收机还包括被配置为基于先前的数据总线电平来选择第一，第二和第三电压基准之一的多路复用逻辑。 其中如果先前数据总线电平为逻辑0，则选择第一参考电压。 如果先前的数据总线电平为逻辑1，则选择第二个参考电压。 如果先前的数据总线电平为三态，则选择第三个参考电压。

公开(公告)号：US08019907B2

公开(公告)日：2011-09-13

申请号：US12753373

申请日：2010-04-02

申请人： Gerald R. Talbot

发明人： Gerald R. Talbot

IPC分类号： G06F13/00 ,  G06F13/12 ,  G06F12/00 ,  G06F3/00

CPC分类号： G06F13/1673

摘要： A memory controller including a dual-mode memory interconnect includes an input/output (I/O) circuit including a plurality of input buffers and a plurality of output drivers. The I/O circuit may be configured to operate in one of a first mode and a second mode dependent upon a state of a mode selection signal. During operation in the first mode, the I/O circuit may be configured to provide a parallel interconnect for connection to one or more memory modules. During operation in the second mode, the I/O circuit may be configured to provide a respective serial interconnect for connection to each of one or more buffer units, each configured to buffer memory data that is being read from or written to the one or more memory modules.

摘要翻译： 包括双模存储器互连的存储器控​​制器包括包括多个输入缓冲器和多个输出驱动器的输入/输出（I / O）电路。 I / O电路可以被配置为依赖于模式选择信号的状态而以第一模式和第二模式中的一个运行。 在第一模式的操作期间，I / O电路可以被配置为提供用于连接到一个或多个存储器模块的并行互连。 在第二模式的操作期间，I / O电路可以被配置为提供用于连接到一个或多个缓冲器单元中的每一个的相应的串行互连，每个缓冲单元被配置为缓冲正被读取或写入到一个或多个缓冲单元的存储器数据 内存模块

公开(公告)号：US07861140B2

公开(公告)日：2010-12-28

申请号：US11590290

申请日：2006-10-31

申请人： Gerald R. Talbot

发明人： Gerald R. Talbot

IPC分类号： G11C29/00

CPC分类号： G06F11/10

摘要： A memory system including asymmetric high-speed differential memory interconnect includes one or more buffer units coupled to one or more memory units such as memory modules, for example, via a parallel interconnect. The memory system also includes a memory controller coupled to each of the buffer units via a respective serial interconnect. The memory controller may control data transfer between the memory controller and the one or more buffer units. During normal operation, each of the buffer units may be configured to receive data from the memory controller via the respective serial interconnect and to transmit the data to the one or more memory units via the parallel interconnect, in response to receiving command information from the memory controller. Further, the memory controller may be configured to modify a phase alignment of information transmitted from the memory controller based upon information received from the buffer units.

摘要翻译： 包括非对称高速差分存储器互连的存储器系统包括一个或多个缓冲单元，例如经由并联互连耦合到一个或多个存储器单元，例如存储器模块。 存储器系统还包括经由相应的串行互连耦合到每个缓冲单元的存储器控​​制器。 存储器控制器可以控制存储器控制器和一个或多个缓冲器单元之间的数据传输。 在正常操作期间，每个缓冲单元可以被配置为经由相应的串行互连从存储器控制器接收数据，并且响应于从存储器接收命令信息，经由并行互连将数据发送到一个或多个存储器单元 控制器。 此外，存储器控制器可以被配置为基于从缓冲器单元接收的信息来修改从存储器控制器发送的信息的相位对准。

公开(公告)号：US07783954B2

公开(公告)日：2010-08-24

申请号：US11518843

申请日：2006-09-11

申请人： Gerald R. Talbot

发明人： Gerald R. Talbot

IPC分类号： H03M13/00

CPC分类号： H04L25/4906 ,  G06F1/10 ,  H04L1/0061 ,  H04L2001/0094

摘要： A system for controlling high-speed bidirectional communication includes a slave device such as a memory device, for example, coupled to a master device such as a memory controller, for example. The master device may be configured to control data transfer between the master device and the slave device. The master device may be configured to provide one or more clock signals to the slave device and during an initialization mode, the master device may modify a phase alignment of the one or more clock signals. Further the master device may subsequently modify a phase alignment of data transmitted from the master device based upon information received from the slave device.

摘要翻译： 用于控制高速双向通信的系统包括例如耦合到诸如存储器控制器的主设备的诸如存储器设备的从设备。 主设备可以被配置为控制主设备和从设备之间的数据传输。 主设备可以被配置为向从设备提供一个或多个时钟信号，并且在初始化模式期间，主设备可以修改一个或多个时钟信号的相位对准。 此外，主设备可以随后基于从从设备接收的信息来修改从主设备发送的数据的相位对准。

公开(公告)号：US20080147897A1

公开(公告)日：2008-06-19

申请号：US11590286

申请日：2006-10-31

申请人： Gerald R. Talbot

发明人： Gerald R. Talbot

IPC分类号： G06F3/00

CPC分类号： G06F13/1673

摘要： A memory controller including a dual-mode memory interconnect includes an input/output (I/O) circuit including a plurality of input buffers and a plurality of output drivers. The I/O circuit may be configured to operate in one of a first mode and a second mode dependent upon a state of a mode selection signal. During operation in the first mode, the I/O circuit may be configured to provide a parallel interconnect for connection to one or more memory modules. During operation in the second mode, the I/O circuit may be configured to provide a respective serial interconnect for connection to each of one or more buffer units, each configured to buffer memory data that is being read from or written to the one or more memory modules.

摘要翻译： 包括双模存储器互连的存储器控​​制器包括包括多个输入缓冲器和多个输出驱动器的输入/输出（I / O）电路。 I / O电路可以被配置为依赖于模式选择信号的状态而以第一模式和第二模式中的一个运行。 在第一模式的操作期间，I / O电路可以被配置为提供用于连接到一个或多个存储器模块的并行互连。 在第二模式的操作期间，I / O电路可以被配置为提供用于连接到一个或多个缓冲器单元中的每一个的相应的串行互连，每个缓冲单元被配置为缓冲正被读取或写入到一个或多个缓冲单元的存储器数据 内存模块

公开(公告)号：US20080104456A1

公开(公告)日：2008-05-01

申请号：US11590290

申请日：2006-10-31

申请人： Gerald R. Talbot

发明人： Gerald R. Talbot

IPC分类号： G06F11/00

CPC分类号： G06F11/10

摘要： A memory system including asymmetric high-speed differential memory interconnect includes one or more buffer units coupled to one or more memory units such as memory modules, for example, via a parallel interconnect. The memory system also includes a memory controller coupled to each of the buffer units via a respective serial interconnect. The memory controller may control data transfer between the memory controller and the one or more buffer units. During normal operation, each of the buffer units may be configured to receive data from the memory controller via the respective serial interconnect and to transmit the data to the one or more memory units via the parallel interconnect, in response to receiving command information from the memory controller. Further, the memory controller may be configured to modify a phase alignment of information transmitted from the memory controller based upon information received from the buffer units.

摘要翻译： 包括非对称高速差分存储器互连的存储器系统包括一个或多个缓冲单元，例如经由并联互连耦合到一个或多个存储器单元，例如存储器模块。 存储器系统还包括经由相应的串行互连耦合到每个缓冲单元的存储器控​​制器。 存储器控制器可以控制存储器控制器和一个或多个缓冲器单元之间的数据传输。 在正常操作期间，每个缓冲单元可以被配置为经由相应的串行互连从存储器控制器接收数据，并且响应于从存储器接收命令信息，经由并行互连将数据发送到一个或多个存储器单元 控制器。 此外，存储器控制器可以被配置为基于从缓冲器单元接收的信息来修改从存储器控制器发送的信息的相位对准。

公开(公告)号：US07227382B1

公开(公告)日：2007-06-05

申请号：US11048440

申请日：2005-02-01

申请人： Gerald R. Talbot ,  Rohit Kumar ,  Stephen C. Hale

发明人： Gerald R. Talbot ,  Rohit Kumar ,  Stephen C. Hale

IPC分类号： H03K19/0175

CPC分类号： H03K19/0005 ,  H04L25/0278

摘要： A driver circuit. In one embodiment, the driver circuit includes a plurality of pull-up circuits and a plurality of pull-down circuits. The driver circuit also includes control logic that is coupled to activate/deactivate the pull-up and pull-down circuits. The driver circuit may perform emphasized signal transmissions having a voltage swing of a first magnitude or de-emphasized signal transmissions having a voltage swing of a second magnitude, wherein the first magnitude is greater than the second magnitude. The control logic is further configured to activate and/or deactivate pull-up and/or pull-down circuits such that the driver circuit output impedance in the emphasized mode is substantially equal to the output impedance in the de-emphasized mode.

摘要翻译： 驱动电路。 在一个实施例中，驱动器电路包括多个上拉电路和多个下拉电路。 驱动器电路还包括耦合以激活/去激活上拉和下拉电路的控制逻辑。 驱动器电路可以执行具有第一幅度的电压摆幅或具有第二幅度的电压摆幅的去加重信号传输的强调信号传输，其中第一幅度大于第二幅度。 控制逻辑还被配置为激活和/或去激活上拉和/或下拉电路，使得强调模式下的驱动电路输出阻抗基本上等于去加重模式中的输出阻抗。

公开(公告)号：US06738917B2

公开(公告)日：2004-05-18

申请号：US09753916

申请日：2001-01-03

申请人： Mark D. Hummel ,  Gerald R. Talbot

发明人： Mark D. Hummel ,  Gerald R. Talbot

IPC分类号： G06F104

CPC分类号： G06F13/4217

摘要： A low latency method of synchronizing asynchronous data to a core clock in a receiving device. A communication referenced to a transmitting clock that is asynchronous to the core clock is received at a receiving device. The communication includes a synchronization signal which is propagated through a synchronizer in the receiving device to synchronize the signal to the core clock. Upon receipt of the synchronization signal by the synchronizer, a load pointer for loading received data into a buffer synchronous with the transmitting clock is reset. Upon completion of the propagation of the synchronization signal through the synchronizer, an unload pointer for unloaded the data from the buffer synchronous with the core clock is reset. The unload pointer is then offset by an amount that compensates for the delay incurred while the synchronization propagated through the synchronizer. Thereafter, the position of the unload pointer is dynamically adjusted based on the accumulated amount of data loaded into the buffer and the accumulated amount of data unloaded from the buffer.

摘要翻译： 将异步数据与接收设备中的核心时钟同步的低延迟方法。 在接收设备处接收参考与核心时钟异步的发送时钟的通信。 通信包括同步信号，其通过接收设备中的同步器传播，以使信号与核心时钟同步。 当同步器接收到同步信号时，复位用于将接收数据加载到与发送时钟同步的缓冲器中的负载指针。 在完成通过同步器的同步信号的传播后，用于从与核心时钟同步的缓冲器中卸载数据的卸载指针被复位。 然后，卸载指针被补偿补偿在通过同步器传播的同步时产生的延迟的量。 此后，基于加载到缓冲器的数据的累积量和从缓冲器卸载的数据的累积量来动态地调整卸载指针的位置。

公开(公告)号：US07929549B1

公开(公告)日：2011-04-19

申请号：US11368786

申请日：2006-03-06

申请人： Gerald R. Talbot

发明人： Gerald R. Talbot

IPC分类号： H04L12/40 ,  G06F12/14 ,  H04L9/00

CPC分类号： H04L12/40013 ,  H04L9/0662

摘要： A memory subsystem includes a master controller that includes a pseudo random bit sequence (PRBS) generator having a plurality of output taps and an exclusive-OR (XOR) unit. The memory subsystem also includes a memory device that is coupled to the master controller via a plurality of single ended bidirectional data paths. The master controller may scramble a plurality of data bits using the PRBS generator and the XOR unit prior to writing the plurality of data bits to the memory device. In addition, the master controller may perform an XOR between each bit of the plurality of data bits and a respective output tap of the PRBS generator prior to conveyance on a respective path of the plurality of single ended bidirectional data paths.

摘要翻译： 存储器子系统包括主控制器，其包括具有多个输出抽头和异或（XOR）单元的伪随机位序列（PRBS）生成器。 存储器子系统还包括经由多个单端双向数据路径耦合到主控制器的存储器件。 在将多个数据位写入存储器件之前，主控制器可以使用PRBS发生器和XOR单元来加扰多个数据位。 此外，主控制器可以在多个单端双向数据路径的相应路径上传输之前，在多个数据位的每一位和PRBS发生器的相应输出抽头之间执行XOR。