公开(公告)号：US07813495B1

公开(公告)日：2010-10-12

申请号：US11183245

申请日：2005-07-16

申请人： Ramsin M. Ziazadeh ,  Vijaya Ceekala

发明人： Ramsin M. Ziazadeh ,  Vijaya Ceekala

IPC分类号： H04M9/00 ,  H04M7/04

CPC分类号： H04B3/235 ,  H04L25/0272

摘要： A communications cabling front-end architecture that achieves solid echo cancellation and lower noise performance by combining an echo-cancellation circuit and an equalizer function at the same point, at the most front-end of the system.

摘要翻译： 通信电缆前端架构，通过在系统最前端的同一点组合回波消除电路和均衡器功能，实现固体回波消除和降低噪声性能。

公开(公告)号：US07208981B1

公开(公告)日：2007-04-24

申请号：US10907904

申请日：2005-04-20

申请人： Ramsin M. Ziazadeh ,  Vijaya Ceekala ,  Matthew James Webb ,  James B. Wieser

发明人： Ramsin M. Ziazadeh ,  Vijaya Ceekala ,  Matthew James Webb ,  James B. Wieser

IPC分类号： H03K5/22

CPC分类号： H04L25/028 ,  H04L1/24 ,  H04L25/0272

摘要： A circuit and method are provided for performing built-in test of output signal magnitudes of integrated differential signal generator circuitry. In accordance with one embodiment, first upper and lower reference voltages and second upper and lower reference voltages are received via a plurality of reference electrodes, wherein: a difference between the first and upper and lower reference voltages comprises a first difference magnitude; a difference between the second upper and lower reference voltages comprises a second difference magnitude; and the first difference magnitude is greater than the second difference magnitude. Test signal generator circuitry provides a plurality of binary signals with respective successions of opposing signal states. Differential signal generator circuitry, coupled to the test signal generator circuitry and responsive to the plurality of binary signals, provides a plurality of differential signals having respective magnitudes related to the respective successions of opposing binary signal states. Signal comparison circuitry, coupled to the plurality of reference electrodes and the differential signal generator circuitry, and responsive to the first and second upper and lower reference signals and the plurality of differential signals, provides a plurality of test signals with respective test signal states indicative of whether respective ones of the differential signal magnitudes are within a range defined as being less than the first difference magnitude and greater than the second difference magnitude.

摘要翻译： 提供了一种电路和方法，用于对集成差分信号发生器电路的输出信号幅值进行内置测试。 根据一个实施例，经由多个参考电极接收第一上参考电压和第二上参考电压和第二上基准电压和下参考电压，其中：第一和上参考电压之间的差包括第一差幅度; 第二上参考电压和下参考电压之间的差包括第二差值; 并且第一差值幅度大于第二差值幅度。 测试信号发生器电路提供具有各自相对的信号状态的多个二进制信号。 耦合到测试信号发生器电路并响应于多个二进制信号的差分信号发生器电路提供具有与相应二进制信号状态的相应序列相关的相应幅度的多个差分信号。 耦合到多个参考电极和差分信号发生器电路并且响应于第一和第二上参考信号和下参考信号和多个差分信号的信号比较电路提供多个测试信号，其中各测试信号状态指示 差分信号幅度中的各个是否在限定为小于第一差分幅度并大于第二差值的范围内。

公开(公告)号：US07369591B1

公开(公告)日：2008-05-06

申请号：US11035686

申请日：2005-01-14

申请人： Ramsin M. Ziazadeh

发明人： Ramsin M. Ziazadeh

IPC分类号： H01S3/00

CPC分类号： H01S5/042 ,  H01S5/0427 ,  H01S5/0683

摘要： A driver for a vertical-cavity surface emitting laser (VCSEL) is provided that includes a bias current source, a modulation source, and a peaking control circuit. The bias current source is operable to generate a bias current for the VCSEL and an output voltage. The modulation current source is coupled to the bias current source by at least one switch and is operable to generate a modulation current for the VCSEL when the switch is closed. The peaking control circuit is coupled to the bias current source. The peaking control circuit is operable to receive the output voltage from the bias current source and to generate a driver output voltage for the VCSEL based on the output voltage. The driver output voltage has less peaking than the output voltage.

摘要翻译： 提供了一种用于垂直腔表面发射激光器（VCSEL）的驱动器，其包括偏置电流源，调制源和峰值控制电路。 偏置电流源可操作以产生VCSEL的偏置电流和输出电压。 调制电流源通过至少一个开关耦合到偏置电流源，并且可操作以在开关闭合时产生用于VCSEL的调制电流。 峰值控制电路耦合到偏置电流源。 峰值控制电路可操作以接收来自偏置电流源的输出电压，并且基于输出电压产生VCSEL的驱动器输出电压。 驱动器输出电压峰值低于输出电压。

公开(公告)号：US07019678B1

公开(公告)日：2006-03-28

申请号：US11036765

申请日：2005-01-14

申请人： Ramsin M. Ziazadeh

发明人： Ramsin M. Ziazadeh

IPC分类号： H03M1/66

CPC分类号： H03M1/742 ,  H03M1/002

摘要： A digital-to-analog converter is provided that includes an input stage and an output stage. The input stage is operable to receive a digital bit of data, to convert the digital bit into a quasi-differential current, and to convert the quasi-differential current into a first voltage using a load that is comprised of transconductance and resistance. The output stage is coupled to the input stage and is operable to generate analog data based on the first voltage.

摘要翻译： 提供了包括输入级和输出级的数模转换器。 输入级可操作以接收数字位数据，将数字位转换为准微分电流，并使用由跨导和电阻组成的负载将准微分电流转换为第一电压。 输出级耦合到输入级，并且可操作以基于第一电压产生模拟数据。

公开(公告)号：US07135902B1

公开(公告)日：2006-11-14

申请号：US10907965

申请日：2005-04-22

申请人： Ramsin M. Ziazadeh ,  Varadarajan Devnath

发明人： Ramsin M. Ziazadeh ,  Varadarajan Devnath

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  G01R31/31725 ,  H03L7/0805

摘要： Integrated differential data signal generator circuitry for providing differential data signals with controlled rise and fall times and built-in test capabilities.

摘要翻译： 集成差分数据信号发生器电路，用于提供具有受控上升和下降时间的差分数据信号和内置测试能力。

公开(公告)号：US06724251B1

公开(公告)日：2004-04-20

申请号：US10244150

申请日：2002-09-12

申请人： Ramsin M. Ziazadeh ,  Jitendra Mohan ,  Abu-Hena Mostafa Kamal

发明人： Ramsin M. Ziazadeh ,  Jitendra Mohan ,  Abu-Hena Mostafa Kamal

IPC分类号： H03F136

CPC分类号： H03F1/0266 ,  H03F1/34

摘要： A circuit with low noise and reduced offset that feeds an input of an opamp with a programmable feedback resistor that provides variable gain settings. Input biasing currents are varied using control bits that are also used to adjust the gain. When the input signal is small (gain at higher setting), a minimum bias current is provided to source the input voltage swing. This scheme reduces the noise and offset generated by the lower transconductance of a biasing transistor while maintaining a constant SNR and fixed offset even in the presence of relatively small input swings. Also, when the input signal is large (gain at lower setting), a maximum bias current can be provided to accommodate the relatively large input swing level. Although the overall noise and offset current are increased for large input swings, the overall SNR and offset is maintained for relatively lower input swings.

摘要翻译： 具有低噪声和偏移偏移的电路，可将运算放大器的输入与可编程反馈电阻器进行输入，从而提供可变增益设置。 使用也用于调整增益的控制位来改变输入偏置电流。 当输入信号较小（较高设定时的增益）时，提供最小偏置电流来输入电压摆幅。 该方案减少了由偏置晶体管的较低跨导产生的噪声和偏移，同时即使在存在相对较小的输入摆幅的情况下也能保持恒定的SNR和固定偏移。 此外，当输入信号较大（在较低设置下的增益）时，可以提供最大偏置电流以适应较大的输入摆幅电平。 尽管对于大的输入摆幅，整体噪声和偏移电流增加，但是对于相对较低的输入摆幅，整体SNR和偏移量保持不变。

公开(公告)号：US07525348B1

公开(公告)日：2009-04-28

申请号：US10907871

申请日：2005-04-19

申请人： Ramsin M. Ziazadeh

发明人： Ramsin M. Ziazadeh

IPC分类号： H03K5/22

CPC分类号： H03K5/2481

摘要： A circuit and method for comparing and providing a signal indicative of a difference in magnitude between a differential signal voltage and a differential reference voltage.

摘要翻译： 一种用于比较和提供指示差分信号电压和差分参考电压之间的幅度差异的信号的电路和方法。

公开(公告)号：US07256651B1

公开(公告)日：2007-08-14

申请号：US11034041

申请日：2005-01-12

申请人： Ramsin M. Ziazadeh ,  Yongseon Koh

发明人： Ramsin M. Ziazadeh ,  Yongseon Koh

IPC分类号： H03F3/45

CPC分类号： H03F3/45237 ,  H03F3/45183 ,  H03F2200/447 ,  H03F2203/45288 ,  H03F2203/45318 ,  H03F2203/45641 ,  H03F2203/45696

摘要： A system and a method are disclosed for providing a constant swing high-gain complementary differential limiting amplifier. High gain for the differential amplifier is created by providing a current to the driving transistors that is a combination of any of (a) constant current, (b) transconductance based current, and (c) temperature compensated based current. A constant differential output swing is created by providing a varying differential current to the output load resistors of the differential amplifier that tracks process and temperature variations within the output load resistors.

摘要翻译： 公开了用于提供恒定摆幅高增益互补差分限幅放大器的系统和方法。 差分放大器的高增益是通过向（a）恒定电流，（b）基于跨导的电流和（c）基于温度补偿的电流）中的任何一个的组合的驱动晶体管提供电流而产生的。 通过向差分放大器的输出负载电阻器提供变化的差分电流来产生恒定的差分输出摆幅，该差分放大器跟踪输出负载电阻器内的过程和温度变化。

公开(公告)号：US07224189B1

公开(公告)日：2007-05-29

申请号：US11036744

申请日：2005-01-14

申请人： Ramsin M. Ziazadeh ,  Jitendra Mohan

发明人： Ramsin M. Ziazadeh ,  Jitendra Mohan

IPC分类号： H03K19/0175

CPC分类号： H03K19/018564 ,  H03K19/09432

摘要： An input network is provided within an integrated circuit for interfacing with signals produced by an external CML driver apparatus. The input network includes an input for receiving the signals, and this input is coupled to a terminating impedance, a DC attenuator and an AC attenuator. A common-mode correction loop is coupled to the AC attenuator and the DC attenuator for rejecting common-mode noise generated by the CML driver apparatus. The common-mode correction loop can also provide a common-mode voltage suitable for facilitating high-speed operation of low-voltage devices in the internal data path of the integrated circuit. An amplifier can be provided to compensate for signal attenuation in the input network.

摘要翻译： 在集成电路内提供输入网络，用于与由外部CML驱动器装置产生的信号进行接口。 输入网络包括用于接收信号的输入，该输入耦合到终端阻抗，直流衰减器和交流衰减器。 共模校正环耦合到AC衰减器和DC衰减器，用于抑制由CML驱动器装置产生的共模噪声。 共模校正环还可以提供适合于促进集成电路的内部数据路径中的低电压器件的高速操作的共模电压。 可以提供放大器来补偿输入网络中的信号衰减。

公开(公告)号：US06606001B1

公开(公告)日：2003-08-12

申请号：US10000195

申请日：2001-10-25

申请人： Ramsin M. Ziazadeh ,  Jitendra Mohan ,  Devnath Varadarajan ,  Vjay Ceekala

发明人： Ramsin M. Ziazadeh ,  Jitendra Mohan ,  Devnath Varadarajan ,  Vjay Ceekala

IPC分类号： H03F304

CPC分类号： H03F3/345 ,  H03F2200/294 ,  H03F2200/372

摘要： There is disclosed high-speed current-mirror circuitry and methods of operating the same. An exemplary impedance-peaking current mirror comprises a N-channel drive transistor and a N-channel mirror transistor. The N-channel drive transistor has a source coupled to ground, a drain coupled to a current source and a gate coupled to the drain via a series connection of a resistor and an inductor. The N-channel mirror transistor has a source coupled to ground, a gate coupled to the drain of the N-channel drive transistor, and a drain coupled to a positive power supply via an impedance load.

摘要翻译： 公开了高速电流镜电路及其操作方法。 示例性的阻抗峰值电流镜包括N沟道驱动晶体管和N沟道镜像晶体管。 N沟道驱动晶体管具有耦合到地的源极，耦合到电流源的漏极和经由电阻器和电感器的串联连接到漏极的栅极。 N沟道反射镜晶体管具有耦合到地的源极，耦合到N沟道驱动晶体管的漏极的栅极和经由阻抗负载耦合到正电源的漏极。