公开(公告)号：US20140163703A1

公开(公告)日：2014-06-12

申请号：US14233715

申请日：2012-07-19

Applicant: Ran Chang ,  Chenguang Liu ,  Aravind Dasu

Inventor： Ran Chang ,  Chenguang Liu ,  Aravind Dasu

IPC: G05D27/02

CPC classification number: G05D27/02 ,  G06K9/00771 ,  G06T7/254 ,  G06T2207/10016 ,  G06T2207/20036 ,  G06T2207/20224 ,  G08B13/19608 ,  G08B13/1961

Abstract: A computer implemented method and system for multi-occupant motion tracking and monitoring may include partitioning out of a controlled space one or more interior regions, tracking one or more occupants within the controlled space by collecting a sequence of images of the controlled space, determining from the sequence of images one or more contiguous pixel groupings corresponding to non-persistent motion (referred to as blobs), and generating one or more bounding boxes that encompass each of the contiguous pixel groupings.

Abstract translation: 用于多人运动跟踪和监测的计算机实现的方法和系统可以包括通过从受控空间中分离一个或多个内部区域，通过收集受控空间的一系列图像来跟踪受控空间内的一个或多个乘客，从 所述图像的序列与非持续运动（称为斑点）对应的一个或多个相邻像素分组，以及生成包含所述连续像素分组中的每一个的一个或多个边界框。

公开(公告)号：US20140226867A1

公开(公告)日：2014-08-14

申请号：US14233935

申请日：2012-07-19

Applicant: Chenguang Liu ,  Ran Chang ,  Bruce Christensen ,  Juan De La Cruz ,  Pranab Banerjee ,  Doug Ahlstrom ,  Aravind Dasu

Inventor： Chenguang Liu ,  Ran Chang ,  Bruce Christensen ,  Juan De La Cruz ,  Pranab Banerjee ,  Doug Ahlstrom ,  Aravind Dasu

IPC: G06T7/20

CPC classification number: G06T7/254 ,  G06Q10/00 ,  G06T2207/10016 ,  G06T2207/20224

Abstract: A computer-implemented method for monitoring and controlling a controlled space. The method includes partitioning a controlled space into one or more regions; evaluating motion within the controlled space; determining occupancy within the one or more regions. The method may also include adjusting conditions within the controlled space based on whether the controlled space, or a specific region thereof, is occupied. Corresponding devices and systems are also disclosed herein.

Abstract translation: 用于监控和控制受控空间的计算机实现的方法。 该方法包括将受控空间划分成一个或多个区域; 评估受控空间内的运动; 确定一个或多个区域内的占用。 该方法还可以包括基于受控空间或其特定区域是否被占用来调整受控空间内的条件。 本文还公开了相应的装置和系统。

公开(公告)号：US20140093130A1

公开(公告)日：2014-04-03

申请号：US14124998

申请日：2012-06-08

Applicant: Aravind Dasu ,  Dean Mathias ,  Chenguang Liu ,  Randy Christensen ,  Bruce Christensen

Inventor： Aravind Dasu ,  Dean Mathias ,  Chenguang Liu ,  Randy Christensen ,  Bruce Christensen

IPC: G06K9/00

CPC classification number: G06K9/00771 ,  G06T7/0008 ,  G06T7/254 ,  G06T2207/30232 ,  G08B13/19606

Abstract: A computer implemented method for sensing occupancy of a workspace includes creating a difference image that represents luminance differences of pixels in past and current images of the workspace resulting from motion in the workspace, determining motion occurring in regions of the workspace based on the difference image, and altering a workspace environment based at least in part on the determined motion. The method also includes determining which pixels in the difference image represent persistent motion that can be ignored and determining which pixels representing motion in the difference image are invalid because the pixels are isolated from other pixels representing motion.

Abstract translation: 一种用于感测工作空间的占用的计算机实现的方法包括创建表示由工作空间中的运动产生的工作空间的过去和当前图像中的像素的亮度差的差分图像，基于差分图像确定在工作区域中发生的运动， 以及至少部分地基于所确定的运动来改变工作空间环境。 该方法还包括确定差异图像中的哪些像素表示可忽略的持续运动，并且由于像素与表示运动的其他像素隔离，并且确定表示差分图像中的运动的哪些像素是无效的。

公开(公告)号：US08831287B2

公开(公告)日：2014-09-09

申请号：US14124998

申请日：2012-06-08

Applicant: Aravind Dasu ,  Dean Mathias ,  Chenguang Liu ,  Randy Christensen ,  Bruce Christensen

Inventor： Aravind Dasu ,  Dean Mathias ,  Chenguang Liu ,  Randy Christensen ,  Bruce Christensen

IPC: G06K9/00 ,  G06T7/20 ,  G06T7/00 ,  G08B13/196

CPC classification number: G06K9/00771 ,  G06T7/0008 ,  G06T7/254 ,  G06T2207/30232 ,  G08B13/19606

Abstract: A computer implemented method for sensing occupancy of a workspace includes creating a difference image that represents luminance differences of pixels in past and current images of the workspace resulting from motion in the workspace, determining motion occurring in regions of the workspace based on the difference image, and altering a workspace environment based at least in part on the determined motion. The method also includes determining which pixels in the difference image represent persistent motion that can be ignored and determining which pixels representing motion in the difference image are invalid because the pixels are isolated from other pixels representing motion.

Abstract translation: 一种用于感测工作空间的占用的计算机实现的方法包括创建表示由工作空间中的运动产生的工作空间的过去和当前图像中的像素的亮度差的差分图像，基于差分图像确定在工作区域中发生的运动， 以及至少部分地基于所确定的运动来改变工作空间环境。 该方法还包括确定差异图像中的哪些像素表示可忽略的持续运动，并且由于像素与表示运动的其他像素隔离，并且确定表示差分图像中的运动的哪些像素是无效的。

公开(公告)号：US08296120B2

公开(公告)日：2012-10-23

申请号：US12489260

申请日：2009-06-22

Applicant: Jonathan D. Phillips ,  Aravind Dasu

Inventor： Jonathan D. Phillips ,  Aravind Dasu

IPC: G06F17/50 ,  G06F9/455 ,  G06G7/48

CPC classification number: G06F17/5054 ,  G06F2217/08

Abstract: Iterative repair problems are generally solved using a combinatorial search method such as simulated annealing are addressed with a FPGA-based coarse-grain pipelined architecture to accelerate a simulated annealing based iterative repair-type event scheduling application. Over 99% of the work done by any simulated annealing algorithm is the repeated execution of three high-level steps: (1) generating, (2) evaluating, and (3) determining the acceptability of a new problem solution. A pipelined processor is designed to take advantage of these steps.

Abstract translation: 迭代修复问题通常使用组合搜索方法（如模拟退火）通过基于FPGA的粗粒度流水线架构来解决，以加速基于模拟退火的迭代修复类型事件调度应用。 超过99％的任何模拟退火算法完成的工作是重复执行三个高级步骤：（1）生成，（2）评估和（3）确定新问题解决方案的可接受性。 流水线处理器被设计为利用这些步骤。

公开(公告)号：US08710864B2

公开(公告)日：2014-04-29

申请号：US13092748

申请日：2011-04-22

Applicant: Aravind Dasu ,  Robert C. Barnes

Inventor： Aravind Dasu ,  Robert C. Barnes

IPC: H03K19/177

CPC classification number: H03K19/17756 ,  G06F15/7867 ,  G06F15/8046

Abstract: A polymorphic systolic array framework that works in conjunction with an embedded microprocessor on an FPGA, that allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms and extendable to more complex applications in the area of aerospace embedded systems.

Abstract translation: 一种与FPGA上的嵌入式微处理器结合使用的多态收缩阵列框架，允许在FPGA上并发激活两种算法的加速度水平的动态和互补扩展。 使用收缩阵列和硬件软件协同设计来获得高效的多应用加速系统。 灵活和简单的框架允许托管更广泛的算法，并可扩展到航空航天嵌入式系统领域更复杂的应用。

公开(公告)号：US20110082994A1

公开(公告)日：2011-04-07

申请号：US12899352

申请日：2010-10-06

Applicant: Aravind Dasu ,  Ramachandra Kallam

Inventor： Aravind Dasu ,  Ramachandra Kallam

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F15/7871 ,  G06F8/654

Abstract: A Partial bitstream relocation method to generates source and destination addresses on Field Programmable Gate Arrays. The bitstream from an active source is located and read in a nonintrusive manner, and written to a destination address. The accelerator runs in real time, moving source code on the fly. Code may be altered by mirror inversion for proper placement when necessary.

Abstract translation: 用于在现场可编程门阵列上生成源地址和目标地址的部分比特流重定位方法。 来自活动源的比特流以非侵入式的方式定位和读取，并被写入目的地地址。 加速器实时运行，动态移动源代码。 代码可以通过镜像反转来更改，以便在必要时进行正确的放置。

公开(公告)号：US20110264888A1

公开(公告)日：2011-10-27

申请号：US13092748

申请日：2011-04-22

Applicant: Aravind Dasu ,  Robert C. Barnes

Inventor： Aravind Dasu ,  Robert C. Barnes

IPC: G06F15/76 ,  G06F9/06

CPC classification number: H03K19/17756 ,  G06F15/7867 ,  G06F15/8046

Abstract: A polymorphic systolic array framework that works in conjunction with an embedded microprocessor on an FPGA, that allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms and extendable to more complex applications in the area of aerospace embedded systems.

Abstract translation: 一种与FPGA上的嵌入式微处理器结合使用的多态收缩阵列框架，允许在FPGA上并发激活两种算法的加速度水平的动态和互补扩展。 使用收缩阵列和硬件软件协同设计，以获得高效的多应用加速系统。 灵活和简单的框架允许托管更广泛的算法，并可扩展到航空航天嵌入式系统领域更复杂的应用。

公开(公告)号：US20070198971A1

公开(公告)日：2007-08-23

申请号：US10544894

申请日：2004-02-05

Applicant: Aravind Dasu ,  Ali Akoglu ,  Arvind Sudarsanam ,  Sethuraman Panchanathan

Inventor： Aravind Dasu ,  Ali Akoglu ,  Arvind Sudarsanam ,  Sethuraman Panchanathan

IPC: G06F9/45

CPC classification number: G06F8/433 ,  G06F8/4432 ,  G06F17/5045 ,  Y02D10/41

Abstract: A method of producing a reconfigurable circuit device for running a computer program of moderate complexity such as multimedia processing. Code for the application is compiled into Control Flow Graphs representing distinct parts of the application to be run. From those Control Flow Graphs are extracted basic blocks. The basic blocks are converted to Data Flow Graphs by a compiler utility. From two or more Data Flow Graphs, a largest common subgraph is determined. The largest common subgraph is ASAP scheduled and substituted back into the Data Flow Graphs which also have been scheduled. The separate Data Flow Graphs containing the scheduled largest common subgraph are converted to data paths that are then combined to form code for operating the application. The largest common subgraph is effected in hardware that is shared among the parts of the application from which the Data Flow Graphs were developed. Scheduling of the overall code is effected for sequencing, providing fastest run times and the code is implemented in hardware by partitioning and placement of processing elements on a chip and design of the connective fabric for the design elements.

Abstract translation: 一种用于运行诸如多媒体处理等中等复杂度的计算机程序的可重构电路装置的方法。 应用程序的代码被编译成表示要运行的应用程序的不同部分的控制流图。 从这些控制流图中提取基本块。 基本块由编译器实用程序转换为数据流图。 从两个或更多数据流图，确定最大的公共子图。 最大的公共子图是ASAP预定的，并被替换为也被安排的数据流图。 包含预定最大公共子图的单独数据流图被转换为数据路径，然后将其组合以形成用于操作应用程序的代码。 最大的共同子图是在开发数据流图的应用程序部分之间共享的硬件实现的。 总体代码的调度受到排序的影响，提供最快的运行时间，并且代码通过在处理元件上分配和放置芯片以及为设计元素设计的连接结构来实现。

公开(公告)号：US20090319253A1

公开(公告)日：2009-12-24

申请号：US12489260

申请日：2009-06-22

Applicant: Jonathan D. Phillips ,  Aravind Dasu

Inventor： Jonathan D. Phillips ,  Aravind Dasu

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F2217/08

Abstract: Iterative repair problems are generally solved using a combinatorial search method such as simulated annealing are addressed with a FPGA-based coarse-grain pipelined architecture to accelerate a simulated annealing based iterative repair-type event scheduling application. Over 99% of the work done by any simulated annealing algorithm is the repeated execution of three high-level steps: (1) generating, (2) evaluating, and (3) determining the acceptability of a new problem solution. A pipelined processor is designed to take advantage of these steps.

Abstract translation: 迭代修复问题通常使用组合搜索方法（如模拟退火）通过基于FPGA的粗粒度流水线架构来解决，以加速基于模拟退火的迭代修复类型事件调度应用。 超过99％的任何模拟退火算法完成的工作是重复执行三个高级步骤：（1）生成，（2）评估和（3）确定新的问题解决方案的可接受性。 流水线处理器被设计为利用这些步骤。