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公开(公告)号：US4263671A
公开(公告)日：1981-04-21
申请号：US952831
申请日：1978-10-19
CPC分类号： H04L7/0058 , H04L7/0062
摘要： A circuit for maintaining proper sampling timing in a data modem wherein main channel equalizer error is correlated with a derivative channel signal to drive a clock correction signal. The derivative channel signal is derived from an equalizer using fewer coefficients than required to derive the main channel equalized signal, and calculation of the equalized derivative and clock correction signal is performed only once every other Baud.
摘要翻译： 一种用于在数据调制解调器中维持适当采样定时的电路，其中主信道均衡器误差与微分信道信号相关以驱动时钟校正信号。 衍生通道信号从均衡器导出，使用比用于导出主信道均衡信号所需的系数更少的系数，并且均衡的微分和时钟校正信号的计算仅每隔一个波特进行一次。
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公开(公告)号：US4213097A
公开(公告)日：1980-07-15
申请号：US952650
申请日：1978-10-19
摘要： An automatic gain control circuit having a coarse analog gain adjustment section producing discrete increments of db gain and a fine digital gain adjustment section. The digital section provides for adjustment of gain through a final increment of db gain to achieve precise gain setting. The output of the digital section is squared and compared to a reference signal to derive an error signal whose value is fed to an apparatus which iteratively determines the precise coarse increment and fine digital settings to achieve the final desired gain setting.
摘要翻译： 一种具有产生db增益的离散增量的粗略模拟增益调整部分和精细数字增益调整部分的自动增益控制电路。 数字部分通过db增益的最终增量来调整增益，以实现精确的增益设置。 数字部分的输出被平方并与参考信号进行比较，以导出其值被馈送到迭代地确定精确的粗增量和精细数字设置以实现最终期望增益设置的装置的误差信号。
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公开(公告)号：US4539689A
公开(公告)日：1985-09-03
申请号：US532155
申请日：1983-09-14
CPC分类号： H04L25/03
摘要： An automatic adaptive equalizer operative on a test pattern including a carrier-only period, clock-only period and a single test impulse. The equalizer employs a transversal filter under control of a microprocessor. Samples of in-phase and quadrature phase components of the received impulse response are cross correlated and autocorrelated to form elements of a complex matrix equation describing the optimum equalizer tap settings. The microprocessor performs a special interative operation utilizing elements of this equation to rapidly and exactly calculate the optimum initial settings for the tap constants. The clock-only portion of the test pattern is analyzed to accurately set a sampling clock to properly sample the received impulse so that matrix formation can be carried out within the duration of the received impulse. Initial equalization can be achieved in a time on the order of 30 milliseconds at a data rate of 9600 bits per second.
摘要翻译： 一种自动自适应均衡器，在包括仅载波周期，仅时钟周期和单个测试脉冲的测试模式下工作。 均衡器在微处理器的控制下采用横向滤波器。 所接收脉冲响应的同相和正交相分量的采样是相互关联的并且是自相关的，以形成描述最佳均衡器抽头设置的复矩阵方程的元素。 微处理器利用该方程的元素执行特殊的交互操作，以快速准确地计算抽头常数的最佳初始设置。 分析测试图案的仅时钟部分以精确地设置采样时钟以对所接收的脉冲进行适当采样，以便可以在所接收脉冲的持续时间内执行矩阵形成。 初始均衡可以在9600比特/秒的数据速率下在大约30毫秒的时间内实现。
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公开(公告)号：US4355402A
公开(公告)日：1982-10-19
申请号：US952856
申请日：1978-10-19
CPC分类号： H03G3/3036 , H04L1/206 , H04L27/08 , H04L27/3809
摘要： Circuitry for detecting and correcting false equilibrium conditions generated in data modems by sudden changes in gain of an associated transmission system including a false gain detector which detects a low rate of production of symbols of largest magnitude and triggers a final gain circuit which initially jumps the overall system gain and thereafter adaptively adjusts the gain jump to the correct value.
摘要翻译： 用于检测和校正在数据调制解调器中产生的虚拟平衡条件的电路，该相关传输系统的增益突然变化，包括检测最大幅度的符号的低生产率的伪增益检测器，并触发最初增益最大的电路 系统增益，然后自适应地调整增益跳转到正确的值。
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