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公开(公告)号：US4263671A
公开(公告)日：1981-04-21
申请号：US952831
申请日：1978-10-19
CPC分类号： H04L7/0058 , H04L7/0062
摘要： A circuit for maintaining proper sampling timing in a data modem wherein main channel equalizer error is correlated with a derivative channel signal to drive a clock correction signal. The derivative channel signal is derived from an equalizer using fewer coefficients than required to derive the main channel equalized signal, and calculation of the equalized derivative and clock correction signal is performed only once every other Baud.
摘要翻译： 一种用于在数据调制解调器中维持适当采样定时的电路，其中主信道均衡器误差与微分信道信号相关以驱动时钟校正信号。 衍生通道信号从均衡器导出，使用比用于导出主信道均衡信号所需的系数更少的系数，并且均衡的微分和时钟校正信号的计算仅每隔一个波特进行一次。
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公开(公告)号：US4539689A
公开(公告)日：1985-09-03
申请号：US532155
申请日：1983-09-14
CPC分类号： H04L25/03
摘要： An automatic adaptive equalizer operative on a test pattern including a carrier-only period, clock-only period and a single test impulse. The equalizer employs a transversal filter under control of a microprocessor. Samples of in-phase and quadrature phase components of the received impulse response are cross correlated and autocorrelated to form elements of a complex matrix equation describing the optimum equalizer tap settings. The microprocessor performs a special interative operation utilizing elements of this equation to rapidly and exactly calculate the optimum initial settings for the tap constants. The clock-only portion of the test pattern is analyzed to accurately set a sampling clock to properly sample the received impulse so that matrix formation can be carried out within the duration of the received impulse. Initial equalization can be achieved in a time on the order of 30 milliseconds at a data rate of 9600 bits per second.
摘要翻译： 一种自动自适应均衡器，在包括仅载波周期，仅时钟周期和单个测试脉冲的测试模式下工作。 均衡器在微处理器的控制下采用横向滤波器。 所接收脉冲响应的同相和正交相分量的采样是相互关联的并且是自相关的，以形成描述最佳均衡器抽头设置的复矩阵方程的元素。 微处理器利用该方程的元素执行特殊的交互操作，以快速准确地计算抽头常数的最佳初始设置。 分析测试图案的仅时钟部分以精确地设置采样时钟以对所接收的脉冲进行适当采样，以便可以在所接收脉冲的持续时间内执行矩阵形成。 初始均衡可以在9600比特/秒的数据速率下在大约30毫秒的时间内实现。
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公开(公告)号：US4355402A
公开(公告)日：1982-10-19
申请号：US952856
申请日：1978-10-19
CPC分类号： H03G3/3036 , H04L1/206 , H04L27/08 , H04L27/3809
摘要： Circuitry for detecting and correcting false equilibrium conditions generated in data modems by sudden changes in gain of an associated transmission system including a false gain detector which detects a low rate of production of symbols of largest magnitude and triggers a final gain circuit which initially jumps the overall system gain and thereafter adaptively adjusts the gain jump to the correct value.
摘要翻译： 用于检测和校正在数据调制解调器中产生的虚拟平衡条件的电路，该相关传输系统的增益突然变化，包括检测最大幅度的符号的低生产率的伪增益检测器，并触发最初增益最大的电路 系统增益，然后自适应地调整增益跳转到正确的值。
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公开(公告)号：US4213097A
公开(公告)日：1980-07-15
申请号：US952650
申请日：1978-10-19
摘要： An automatic gain control circuit having a coarse analog gain adjustment section producing discrete increments of db gain and a fine digital gain adjustment section. The digital section provides for adjustment of gain through a final increment of db gain to achieve precise gain setting. The output of the digital section is squared and compared to a reference signal to derive an error signal whose value is fed to an apparatus which iteratively determines the precise coarse increment and fine digital settings to achieve the final desired gain setting.
摘要翻译： 一种具有产生db增益的离散增量的粗略模拟增益调整部分和精细数字增益调整部分的自动增益控制电路。 数字部分通过db增益的最终增量来调整增益，以实现精确的增益设置。 数字部分的输出被平方并与参考信号进行比较，以导出其值被馈送到迭代地确定精确的粗增量和精细数字设置以实现最终期望增益设置的装置的误差信号。
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公开(公告)号：US4455665A
公开(公告)日：1984-06-19
申请号：US304044
申请日：1981-09-21
CPC分类号： H04L7/027
摘要： A digital timing recovery circuit operative upon digital samples of the input signal to a data receiver provided at the sample rate to produce a clock correction signal at the symbol rate utilizing a digital periodic filter providing a double restrictive bandpass characteristic about the band edge frequencies and outputting to a nonlinear device followed by a digital sampling filter designed to require only addition and subtraction of the nonlinear device outputs.
摘要翻译： 一种数字定时恢复电路，其操作在输入信号的数字采样到以采样率提供的数据接收器，以便以符号率产生时钟校正信号，利用数字周期滤波器提供关于频带边缘频率的双重限制带通特性并输出 到非线性器件，其后是数字采样滤波器，其被设计为仅需要非线性器件输出的加法和减法。
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公开(公告)号：US4658210A
公开(公告)日：1987-04-14
申请号：US626315
申请日：1984-06-29
CPC分类号： G01R29/26
摘要： A noninterruptive noise measurement technique wherein the absolute value of the amplitude error from a modem slicer is compared to a reference, the number of events in excess of said reference over a selected interval are counted and the range within which said count falls is determined as a particular signal to noise ratio value.
摘要翻译： 一种非中断噪声测量技术，其中将来自调制解调器限幅器的振幅误差的绝对值与参考值进行比较，对选定间隔中超过所述参考的事件数进行计数，并将所述计数下降的范围确定为 特定的信噪比值。
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7.发明授权Microprocessor architecture employing efficient operand and instruction addressing 失效采用高效操作数和指令寻址的微处理器架构
公开(公告)号：US4541045A
公开(公告)日：1985-09-10
申请号：US304017
申请日：1981-09-21
CPC分类号： G06F9/355 , G06F9/3802 , G06F9/3824 , G06F9/3867
摘要： A two-bus, two instruction type, pipelined microprocessor having a control means which orders application of instruction and data addresses to a memory and further interleaves instructions and data on a single bus to achieve maximum efficiency in operation.
摘要翻译： 一种双总线两种指令类型的流水线微处理器，其具有控制装置，该控制装置将指令和数据地址的应用命令给存储器，并且进一步交织单个总线上的指令和数据以实现最大的操作效率。
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公开(公告)号：US4601044A
公开(公告)日：1986-07-15
申请号：US548572
申请日：1983-11-04
CPC分类号： H04L27/3433 , H04L27/00 , H04L27/3438 , H04L27/3818 , H04L27/3872
摘要： Disclosed is a modulation-demodulation system and method for transmitting a plurality of sequentially received information bit sequences, the system including a transmitter having a state machine for expanding by a coding process each information bit sequence into an expanded bit sequence with a coded bit group portion and, in some cases, an uncoded bit group portion. The transmitter further includes a modulator for modulating a carrier signal by one of a plurality of multilevel symbols in a two-dimensional complex plane in response to each sequentially applied expanded bit sequence, with the coded bit group portion being used to specify a subset of the multilevel symbols which when rotated in the complex plane maps upon another subset for each adverse angular rotation and the uncoded bit group portion being used to specify for a selected multiple symbol subset the transmitted multilevel symbol of the carrier signal. The system further includes a receiver having a demodulator and slicer for demodulating and detecting the modulated carrier signal to obtain the expanded bit sequences; a phase rotation detector, coupled to the slicer, for uniquely identifying each adverse angular rotation by analyzing a plurality of sequentially applied coded bit group portions; and a phase corrector, coupled to the phase rotation detector, for compensating for the adverse angular rotation.
摘要翻译： 公开了一种用于发送多个顺序接收的信息比特序列的调制解调系统和方法，该系统包括具有状态机的发射机，用于通过编码处理将每个信息比特序列扩展为具有编码比特组部分的扩展比特序列 并且在一些情况下，是未编码的位组部分。 所述发射机还包括调制器，用于响应于每个顺序应用的扩展比特序列，在二维复平面中的多个多电平符号中的一个调制载波信号，所述编码比特组部分用于指定所述载波信号的子集 当在复平面中旋转时，多级符号映射到每个不利角旋转的另一子集，并且未编码位组部分被用于为所选择的多符号子集指定所传输的载波信号的多电平符号。 该系统还包括具有用于解调和检测调制载波信号以获得扩展比特序列的解调器和限幅器的接收机; 相位旋转检测器，耦合到限幅器，用于通过分析多个顺序施加的编码位组部分来唯一地识别每个不利的角旋转; 以及相位校正器，耦合到相位旋转检测器，用于补偿不利的角旋转。
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