Memory system with both single and consolidated commands
    1.
    发明申请
    Memory system with both single and consolidated commands 有权
    具有单一和统一命令的内存系统

    公开(公告)号:US20070150687A1

    公开(公告)日:2007-06-28

    申请号:US11318028

    申请日:2005-12-23

    IPC分类号: G06F13/00

    CPC分类号: G06F13/1642 Y02D10/14

    摘要: In some embodiments, a chip includes a request queue to include write requests, and scheduling circuitry to schedule commands including commands in response to the write requests. The chip also includes mode selection circuitry to monitor the request queue and in response thereto to select a first or a second mode for the scheduling circuitry, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules consolidated commands to represent more than one separate single command. Other embodiments are described.

    摘要翻译: 在一些实施例中,芯片包括包括写入请求的请求队列,以及调度电路来调度包括响应于写入请求的命令的命令。 芯片还包括模式选择电路,用于监视请求队列并响应于此选择用于调度电路的第一或第二模式,其中在第一模式中,调度电路将某些命令调度为单独的单个命令,并且在第二模式中 调度电路安排统一的命令来表示多个独立的单个命令。 描述其他实施例。

    Chips providing single and consolidated commands
    2.
    发明申请
    Chips providing single and consolidated commands 有权
    芯片提供单一和统一的命令

    公开(公告)号:US20070150688A1

    公开(公告)日:2007-06-28

    申请号:US11491312

    申请日:2006-07-21

    IPC分类号: G06F13/28

    CPC分类号: G06F13/1642 Y02D10/14

    摘要: In some embodiments, a chip includes a link interface, monitoring circuitry to provide an activity indicator that is indicative of activity of the chip, and scheduling circuitry to schedule commands. The chip also includes mode selection circuitry to select a first mode or a second mode for the scheduling circuitry depending on the activity indicator, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules at least one consolidated command to represent more than one of the separate single commands. Other embodiments are described.

    摘要翻译: 在一些实施例中,芯片包括链路接口,监控电路,用于提供指示芯片的活动的活动指示符,以及调度电路来调度命令。 芯片还包括模式选择电路,用于根据活动指示器为调度电路选择第一模式或第二模式,其中在第一模式中,调度电路将某些命令调度为单独的单个命令,并且在第二模式中,调度电路调度 至少一个统一命令来表示多个单独的单个命令。 描述其他实施例。

    Chips providing single and consolidated commands
    4.
    发明授权
    Chips providing single and consolidated commands 有权
    芯片提供单一和统一的命令

    公开(公告)号:US07752411B2

    公开(公告)日:2010-07-06

    申请号:US11491312

    申请日:2006-07-21

    IPC分类号: G06F12/00 G06F13/00 G06F13/28

    CPC分类号: G06F13/1642 Y02D10/14

    摘要: In some embodiments, a chip includes a link interface, monitoring circuitry to provide an activity indicator that is indicative of activity of the chip, and scheduling circuitry to schedule commands. The chip also includes mode selection circuitry to select a first mode or a second mode for the scheduling circuitry depending on the activity indicator, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules at least one consolidated command to represent more than one of the separate single commands. Other embodiments are described.

    摘要翻译: 在一些实施例中,芯片包括链路接口,监控电路,用于提供指示芯片的活动的活动指示符,以及调度电路来调度命令。 芯片还包括模式选择电路,用于根据活动指示器为调度电路选择第一模式或第二模式,其中在第一模式中,调度电路将某些命令调度为单独的单个命令,并且在第二模式中,调度电路调度 至少一个统一命令来表示多个单独的单个命令。 描述其他实施例。

    Memory system with both single and consolidated commands
    5.
    发明授权
    Memory system with both single and consolidated commands 有权
    具有单一和统一命令的内存系统

    公开(公告)号:US07673111B2

    公开(公告)日:2010-03-02

    申请号:US11318028

    申请日:2005-12-23

    IPC分类号: G06F12/00 G06F13/00 G06F13/28

    CPC分类号: G06F13/1642 Y02D10/14

    摘要: In some embodiments, a chip includes a request queue to include write requests, and scheduling circuitry to schedule commands including commands in response to the write requests. The chip also includes mode selection circuitry to monitor the request queue and in response thereto to select a first or a second mode for the scheduling circuitry, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules consolidated commands to represent more than one separate single command. Other embodiments are described.

    摘要翻译: 在一些实施例中,芯片包括包括写入请求的请求队列,以及调度电路来调度包括响应于写入请求的命令的命令。 芯片还包括模式选择电路,用于监视请求队列并响应于此选择用于调度电路的第一或第二模式,其中在第一模式中,调度电路将某些命令调度为单独的单个命令,并且在第二模式中 调度电路安排统一的命令来表示多个独立的单个命令。 描述其他实施例。