公开(公告)号：US06389529B1

公开(公告)日：2002-05-14

申请号：US09344059

申请日：1999-06-25

申请人： Ravi Kumar Arimilli ,  Lakshminarayanan Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  Lakshminarayanan Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F9312

CPC分类号： G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384

摘要： A system for time-ordered execution of load instructions. More specifically, the system enables just-in-time delivery of data requested by a load instruction. The system consists of a processor, an L1 data cache with corresponding L1 cache controller, and an instruction processor. The instruction processor manipulates a plurality of architected time dependency fields of a load instruction to create a plurality of dependency fields. The dependency fields holds a relative dependency value which is utilized to order the load instruction in a Relative Time-Ordered Queue (RTOQ) of the L1 cache controller. The load instruction is sent from RTOQ to the L1 data cache at a particular time so that the data requested is loaded from the L1 data cache at the time specified by one of the dependency fields. The dependency fields are prioritized so that the cycle corresponding to the highest priority field which is available is utilized.

摘要翻译： 用于加载指令的时间执行的系统。 更具体地，该系统实现了由加载指令请求的数据的及时传送。 该系统由处理器，具有对应的L1高速缓存控制器的L1数据高速缓存器和指令处理器组成。 指令处理器操纵加载指令的多个架构时间依赖性字段以创建多个依赖项。 相关性字段保持相对依赖性值，该相关性值用于对L1高速缓存控制器的相对时间排序队列（RTOQ）中的加载指令进行排序。 加载指令在特定时间从RTOQ发送到L1数据高速缓存，以便在由一个依赖项指定的时间内从L1数据高速缓存中加载请求的数据。 优先依赖关系字段，以便利用对应于可用的最高优先级字段的周期。

公开(公告)号：US06430683B1

公开(公告)日：2002-08-06

申请号：US09344023

申请日：1999-06-25

申请人： Ravi Kumar Arimilli ,  Lakshminarayanan Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  Lakshminarayanan Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F9312

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3838 ,  G06F12/0855 ,  G06F12/0859 ,  G06F13/4217

摘要： A system for time-ordered execution of load instructions. More specifically, the system enables just-in-time delivery of data requested by a load instruction. The system consists of a processor, an L1 data cache with corresponding L1 cache controller, and an instruction processor. The instruction processor manipulates an architected time dependency bit field of a load instruction to create a Distance of Dependency (DoD) bit field. The DoD bit field holds a relative dependency value which is utilized to order the load instruction in a Relative Time-Ordered Queue (RTOQ) of the L1 cache controller. The load instruction is sent from RTOQ to the L1 data cache at a particular time so that the data requested is loaded from the L1 data cache at the time specified by the DoD bit field. In the preferred embodiment, an acknowledgement is sent to the processing unit when the time specified is available in the RTOQ.

摘要翻译： 用于加载指令的时间执行的系统。 更具体地，该系统实现了由加载指令请求的数据的及时传送。 该系统由处理器，具有对应的L1高速缓存控制器的L1数据高速缓存器和指令处理器组成。 指令处理器操纵负载指令的架构化时间依赖性位字段以创建依赖距离（DoD）位字段。 DoD位域保持相对依赖性值，该值用于对L1高速缓存控制器的相对时间排序队列（RTOQ）中的加载指令进行排序。 加载指令在特定时间从RTOQ发送到L1数据高速缓存，以便在DoD位字段指定的时间从L1数据高速缓存中加载请求的数据。 在优选实施例中，当指定的时间在RTOQ中可用时，确认被发送到处理单元。

公开(公告)号：US06425090B1

公开(公告)日：2002-07-23

申请号：US09338946

申请日：1999-06-25

申请人： Ravi Kumar Arimilli ,  Lakshminarayanan Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  Lakshminarayanan Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F104

CPC分类号： G06F9/3836 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/384

摘要： A method for converting a distance of dependency (DoD) value to a cycle of dependency (CoD) value is disclosed. The method comprises the steps of (i) simulating a dependency system timer (DST) on a data processing system, with the DST having a present time measured in cycles and a period, (ii) adding a DoD value of N bits to the present time to yield a resulting time of the least significant N bits of said adding step, and (iii) creating the CoD value by appending a carry over of the adding step to the resulting time, where when the carry over is not equal to zero, the carry over signals a user of the CoD value to wait until a next period before the CoD value should be applied. In one embodiment, the carry-over value is added to the value corresponding to a respective alternating period to yield an even/odd bit which determines the period.

摘要翻译： 公开了将依赖距离（DoD）值转换为依赖循环（CoD）值的方法。 该方法包括以下步骤：（i）在数据处理系统上模拟依赖系统定时器（DST），其中DST具有以周期和周期测量的当前时间，（ii）向目前添加N位的DoD值 时间以产生所述相加步骤的最低有效N比特的结果时间，以及（iii）通过将加法步骤的进位附加到所得到的时间来创建CoD值，其中当进位不等于零时， 进位信号指示CoD值的用户等待直到应用CoD值之前的下一个周期。 在一个实施例中，结转值被加到对应于相应交替周期的值，以产生确定周期的偶数/奇数位。

公开(公告)号：US06397320B1

公开(公告)日：2002-05-28

申请号：US09344061

申请日：1999-06-25

申请人： Ravi Kumar Arimilli ,  Lakshminarayanan Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  Lakshminarayanan Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F9312

CPC分类号： G06F9/30043 ,  G06F9/383 ,  G06F12/0811 ,  G06F12/0859

摘要： A method for ordering the time of issuing of a load instruction from a lower level (L2) cache controller to its L2 cache in a data processing system to enable delivery of a load data at a time it is required by its downstream dependency is disclosed. The method comprises the steps of (i) determining a cycle of dependency (CoD) of the load data, where the CoD corresponds to an exact synchronized timer (ST) time, measured in cycles, on which said data is required by said downstream dependency from the L2 cache, and (ii) issuing the load instruction to said L2 cache at said time to synchronize a providing of said data to a pipeline of a system resource with a request by its downstream dependency. In the preferred embodiment of the invention, a distance of dependency (DoD) value is first appended to the load instruction. The DoD value is then converted to a CoD value when a miss occurs at the internal (L1) cache.

摘要翻译： 公开了一种在数据处理系统中排序从下一级（L2）高速缓存控制器向其二级高速缓存发出加载指令的时间的方法，以便能够在其下游依赖性所需的时间传送负载数据。 该方法包括以下步骤：（i）确定负载数据的依赖循环（CoD），其中CoD对应于以周期测量的精确同步定时器（ST）时间，所述下行依赖性需要所述数据 以及（ii）在所述时间向所述L2高速缓存发出加载指令，以使所述数据与系统资源的流水线通过其下游依赖关系的请求同步。 在本发明的优选实施例中，首先将依赖距离（DoD）值附加到加载指令。 当内部（L1）缓存发生未命中时，DoD值被转换为CoD值。

公开(公告)号：US06427204B1

公开(公告)日：2002-07-30

申请号：US09344058

申请日：1999-06-25

申请人： Ravi Kumar Arimilli ,  Lakshminarayanan Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  Lakshminarayanan Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F938

CPC分类号： G06F9/3802 ,  G06F12/0875

摘要： A system for time-ordered issuance of instruction fetch requests (IFR). More specifically, the system enables just-in-time delivery of instructions requested by an IFR. The system consists of a processor, an L1 instruction cache with corresponding L1 cache controller, and an instruction processor. The instruction processor manipulates an architected time dependency field of an IFR to create a Time of Dependency (ToD) field. The ToD field holds a time dependency value which is utilized to order the IFR in a Relative Time-Ordered Queue (RTOQ) of the L1 cache controller. The IFR is issued from RTOQ to the L1 instruction cache so that the requested instruction is fetched from the L1 instruction cache at the time specified by the ToD value. In an alternate embodiment the ToD is converted to a CoD and the instruction is fetched from a lower level cache at the CoD value.

摘要翻译： 用于定时发出指令提取请求（IFR）的系统。 更具体地说，该系统能够及时交付IFR所要求的指令。 该系统由处理器，具有相应的L1高速缓存控制器的L1指令高速缓存器和指令处理器组成。 指令处理器操纵IFR的架构化时间依赖性字段以创建依赖时间（ToD）字段。 ToD字段保留时间依赖性值，该值用于在L1高速缓存控制器的相对时间排序队列（RTOQ）中排序IFR。 IFR从RTOQ发送到L1指令高速缓存，以便在由ToD值指定的时间内从L1指令高速缓存中取出所请求的指令。 在替代实施例中，ToD被转换为CoD，并且以CoD值从较低级别的高速缓存取出指令。

公开(公告)号：US06393553B1

公开(公告)日：2002-05-21

申请号：US09344060

申请日：1999-06-25

申请人： Ravi Kumar Arimilli ,  Lakshminarayanan Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  Lakshminarayanan Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F9312

CPC分类号： G06F9/30043 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384

摘要： A system which permits dynamic verification of the availability of a desired time at which to load a data requested by a load instruction. The system comprises (i) means for appending a time dependency value to the load instruction, where the time dependency value corresponds to the desired time, (ii) means for verifying that said desired time is available for loading said data, and (iii) means for sending an acknowledgement (ACK) when the desired time is available, where a processor reserves the system resources for accepting the data at the desired time in response to the ACK.

摘要翻译： 允许动态验证加载由加载指令请求的数据的期望时间的可用性的系统。 该系统包括（i）用于将时间依赖性值附加到加载指令的装置，其中时间依赖性值对应于所需时间，（ii）用于验证所述期望时间可用于加载所述数据的装置，以及（iii） 用于当期望的时间可用时发送确认（ACK）的装置，其中处理器保留用于响应于该ACK的期望时间接收数据的系统资源。

公开(公告)号：US06516368B1

公开(公告)日：2003-02-04

申请号：US09435928

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jody B. Joyner ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jody B. Joyner ,  Jerry Don Lewis

IPC分类号： G06F1314

CPC分类号： G06F12/0831

摘要： In response to a need to initiate one or more global operations, a bus master within a multiprocessor system issues a combined token and operation request in a single bus transaction on a bus coupled to the bus master. The combined token and operation request solicits a single existing token required to complete the global operations within the multiprocessor system and identifies the first of the global operations to be processed with the token, if granted. Once a bus master is granted the token, no other bus master will be granted the token until the current token owner explicitly requests release. The current token owner repeats the combined token and operation request for each global operation which needs to be initiated and, on the last global operation, issues a combined request with an explicit release. Acknowledgement of the combined request with release implies release of the token for use by other bus masters.

摘要翻译： 响应于需要启动一个或多个全局操作，多处理器系统内的总线主机在耦合到总线主机的总线上的单总线事务中发出组合令牌和操作请求。 组合的令牌和操作请求请求在多处理器系统中完成全局操作所需的单个现有令牌，并且如果被授予则标识要使用令牌处理的第一个全局操作。 一旦总线主机被授予令牌，在当前令牌所有者明确请求发布之前，将不会授予其他总线主机的令牌。 当前的标记所有者重复需要启动的每个全局操作的组合令牌和操作请求，并且在最后一个全局操作中发出具有明确版本的组合请求。 对发布的组合请求的确认意味着释放令牌供其他总线主机使用。

公开(公告)号：US06460100B1

公开(公告)日：2002-10-01

申请号：US09435929

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jody B. Joyner ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jody B. Joyner ,  Jerry Don Lewis

IPC分类号： G06F1314

CPC分类号： G06F13/37

摘要： Only a single snooper queue for global operations within a multiprocessor system is implemented within each bus snooper, controlled by a single token allowing completion of one operation. A bus snooper, upon detecting a combined token and operation request, begins speculatively processing the operation if the snooper is not already busy. The snooper then watches for a combined response acknowledging the combined request or a subsequent token request from the same processor, which indicates that the originating processor has been granted the sole token for completing global operations, before completing the operation. When processing an operation from a combined request and detecting an operation request (only) from a different processor, which indicates that another processor has been granted the token, the snooper suspends processing of the current operation and begins processing the new operation. If the snooper is busy when a combined request is received, the snooper retries the operation portion of the combined request and, upon detecting a subsequent operation request (only) for the operation, begins processing the operation at that time if not busy. Snoop logic for large multiprocessor systems is thus simplified, with conflict reduced to situations in which multiple processors are competing for the token.

摘要翻译： 在一个多处理器系统内，只有一个用于全局操作的侦听队列是在每个总线侦听器中实现的，由一个允许完成一个操作的令牌控制。 一旦检测到组合的令牌和操作请求，总线侦听器开始推测性地处理该操作，如果该侦听器尚未忙。 监听器然后在完成操作之前监视来自同一处理器的组合请求或后续令牌请求的组合响应，其指示始发处理器已经被授予用于完成全局操作的唯一令牌。 当从组合请求处理操作并从另一处理器（仅指示另一个处理器已被授予令牌）检测到操作请求时，监听器暂停对当前操作的处理并开始处理新的操作。 如果接收到组合请求时，监听器正忙，则侦听器重试组合请求的操作部分，并且在检测到用于该操作的后续操作请求（仅））时，如果不忙，则开始处理该操作。 因此，大型多处理器系统的窥探逻辑被简化，冲突降低到多个处理器竞争令牌的情况。

公开(公告)号：US06347363B1

公开(公告)日：2002-02-12

申请号：US09024316

申请日：1998-02-17

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F1208

CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/123

摘要： Logically in line caches within a multilevel cache hierarchy are jointly controlled by single cache controller. By combining the cache controller and snoop logic for different levels within the cache hierarchy, separate queues are not required for each level. During a cache access, cache directories are looked up in parallel. Data is retrieved from an upper cache if hit, or from the lower cache if the upper cache misses and the lower cache hits. LRU units may be updated in parallel based on cache directory hits. Alternatively, the lower cache LRU unit may be updated based on cache memory accesses rather than cache directory hits, or the cache hierarchy may be provided with user selectable modes of operation for both LRU unit update schemes. The merged vertical cache controller mechanism does not require the lower cache memory to be inclusive of the upper cache memory. A novel deallocation scheme and update protocol may be implemented in conjunction with the merged vertical cache controller mechanism.

摘要翻译： 逻辑上在多级缓存层次结构中的行高速缓存由单缓存控制器联合控制。 通过将缓存控制器和窥探逻辑组合在缓存层次结构中的不同级别，每个级别不需要单独的队列。 在缓存访问期间，并行查找缓存目录。 如果命中，则从高级缓存中检索数据，如果高速缓存未命中，并且较低级缓存命中，则从较低级缓存中检索数据。 可以基于缓存目录命中并行更新LRU单元。 或者，可以基于高速缓存存储器访问而不是高速缓存目录命中来更新低级缓存LRU单元，或者可以为两个LRU单元更新方案提供用户可选择的操作模式的高速缓存层级。 合并的垂直高速缓存控制器机制不需要较低的高速缓冲存储器来包含高速缓存存储器。 可以结合合并的垂直高速缓存控制器机制来实现新颖的解除分配方案和更新协议。

公开(公告)号：US06338124B1

公开(公告)日：2002-01-08

申请号：US09368229

申请日：1999-08-04

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Jody B. Joyner ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Jody B. Joyner ,  Jerry Don Lewis

IPC分类号： G06F1208

CPC分类号： G06F12/123 ,  G06F12/0831

摘要： Combined response logic for a bus receives a combined data access and cast out/deallocate operation initiating by a storage device within a specific level of a storage hierarchy, with a coherency state and LRU position of the cast out/deallocate victim appended. Snoopers on the bus drive snoop responses to the combined operation with the coherency state and/or LRU position of locally-stored cache lines corresponding to the victim appended. The combined response logic determines, from the coherency state and LRU position information appended to the combined operation and the snoop responses, whether an update of the LRU position and/or coherency state of a cache line corresponding to the victim within one of the snoopers is required. If so, the combined response logic selects a snooper storage device to have at least the LRU position of a respective cache line corresponding to the victim updated, and appends an update command identifying the selected snooper to the combined response. The snooper selected to be updated may be randomly chosen, selected based on LRU position of the cache line corresponding to the victim within respective storage, or selected based on other criteria.

摘要翻译： 总线的组合响应逻辑接收组合的数据访问，并且通过由存储层级的特定级别中的存储设备发起/撤销分配操作，附加了外推/解除分配的受害者的一致性状态和LRU位置。 总线驱动器侦听器上的侦听器响应于与所附加的受害者对应的本地存储的缓存线的相关性状态和/或LRU位置的组合操作。 组合响应逻辑从相关性状态和附加到组合操作和窥探响应的LRU位置信息中确定与窥探者之一内的受害者对应的高速缓存线的LRU位置和/或一致性状态的更新是否是 需要。 如果是，组合的响应逻辑选择窥探存储设备至少具有与受害者相对应的相应高速缓存行的LRU位置更新，并且将识别所选窥探者的更新命令附加到组合响应。 选择要更新的窥探者可以被随机地选择，基于在相应存储器内对应于受害者的高速缓存线的LRU位置来选择，或者基于其他标准来选择。