公开(公告)号：US5185736A

公开(公告)日：1993-02-09

申请号：US351861

申请日：1989-05-12

申请人： Raymond E. Tyrrell ,  O. Lamar Bishop ,  William E. Powell ,  Dale L. Krisher ,  William H. Stephenson ,  M. Rodney Briscoe ,  Hal A. Thorne ,  Claude M. Hurlocker ,  V. Paul Runyon ,  Timothy J. Williams ,  Joseph E. Sutherland ,  William B. Weeber ,  Michael J. Gingell ,  Kenneth J. Stoia ,  William J. Fox ,  Jeffrey P. Jones ,  Richard M. Czerwiec ,  Ertugrul Baydar ,  Heinrich T. Sonnenberg ,  Richard Peters ,  Gus C. Sanders ,  Richard J. Sanders, Jr. ,  Francis G. Noser ,  Joseph L. Smith ,  Jak Yaemsiri ,  Camille A. Abu-Saba ,  Patrick M. Farrell ,  Wenkwei Rou ,  Victor W. Wilkerson ,  Mohammad S. Arani ,  Stephen C. Dunning ,  Keith Bernhardt ,  Dana Merrill ,  Michael Sutton

发明人： Raymond E. Tyrrell ,  O. Lamar Bishop ,  William E. Powell ,  Dale L. Krisher ,  William H. Stephenson ,  M. Rodney Briscoe ,  Hal A. Thorne ,  Claude M. Hurlocker ,  V. Paul Runyon ,  Timothy J. Williams ,  Joseph E. Sutherland ,  William B. Weeber ,  Michael J. Gingell ,  Kenneth J. Stoia ,  William J. Fox ,  Jeffrey P. Jones ,  Richard M. Czerwiec ,  Ertugrul Baydar ,  Heinrich T. Sonnenberg ,  Richard Peters ,  Gus C. Sanders ,  Richard J. Sanders, Jr. ,  Francis G. Noser ,  Joseph L. Smith ,  Jak Yaemsiri ,  Camille A. Abu-Saba ,  Patrick M. Farrell ,  Wenkwei Rou ,  Victor W. Wilkerson ,  Mohammad S. Arani ,  Stephen C. Dunning ,  Keith Bernhardt ,  Dana Merrill ,  Michael Sutton

IPC分类号： H04J3/08 ,  H04J3/16 ,  H04Q11/04

CPC分类号： H04J3/1611 ,  H04J3/08 ,  H04J2203/0048 ,  H04J2203/006

摘要： A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

公开(公告)号：US5161152A

公开(公告)日：1992-11-03

申请号：US452291

申请日：1989-12-15

申请人： Richard M. Czerwiec ,  Raymond E. Tyrrell ,  Gus C. Sanders ,  Joseph E. Sutherland ,  Richard J. Sanders, Jr. ,  Claude M. Hurlocker ,  Hal A. Thorne ,  V. Paul Runyon ,  Enn Aro

发明人： Richard M. Czerwiec ,  Raymond E. Tyrrell ,  Gus C. Sanders ,  Joseph E. Sutherland ,  Richard J. Sanders, Jr. ,  Claude M. Hurlocker ,  Hal A. Thorne ,  V. Paul Runyon ,  Enn Aro

IPC分类号： H04J3/16 ,  H04L12/52 ,  H04Q11/04

CPC分类号： H04Q11/04 ,  H04J3/1611 ,  H04L12/52

摘要： A terminal for a telecommunications system provides access to one or two high-speed synchronous transmission lines by both low-speed transmission lines and subscriber lines. A core module includes interfaces to the high-speed lines, a time slot interchanger, an interface to the low-speed transmission lines, processors and overhead circuitry for supporting the terminal. An access module includes a plurality of line shelves connected to subscriber lines, each line shelf includes a pair of processors and for time slot assignors. A multi-link serial bus connects the time slot interchanger to the access module and to the low-speed interface and provides close coupling between the processors in the core module and the line shelves. The processors cooperate to groom subscriber information from said subscriber lines to and from time slots in said high-speed feeder line and said low-speed transmission line. Subscriber information may also be groomed between time slots of the high-speed feeder line and the low-speed transmission lines and between time slots within each subscriber line.

公开(公告)号：US5027349A

公开(公告)日：1991-06-25

申请号：US547383

申请日：1990-07-03

申请人： Hal A. Thorne

发明人： Hal A. Thorne

IPC分类号： H04L29/06

CPC分类号： H04L29/06

摘要： A control method and apparatus for an electronic system having a plurality of functional elements, both intelligent and non-intelligent, interconnected by a plurality of time-division multiplexed serial data links, wherein information is normally conveyed in time slots on the data links. Control information is exchanged between the elements by using one or more of said time slots as control channels for all control information. The format of the control information is compatible with both the intelligent elements and non-intelligent elements. The control information format includes a plurality of bits for providing command data, a plurality of address bits, a valid bit to indicate that the information being transmitted is a valid message, an interrupt bit to signal a microprocessor in an intelligent device to interrupt and service the message, and a parity bit for error checking.

摘要翻译： 一种用于电子系统的控制方法和装置，具有通过多个时分复用串行数据链路互连的智能和非智能的多个功能元件，其中信息通常在数据链路上的时隙中传送。 通过使用一个或多个所述时隙作为所有控制信息的控制信道，在元件之间交换控制信息。 控制信息的格式与智能元件和非智能元件兼容。 控制信息格式包括用于提供命令数据的多个位，多个地址位，用于指示被发送的信息是有效消息的有效位，用于发送智能设备中的微处理器的中断和服务的中断位 消息和用于错误检查的奇偶校验位。