公开(公告)号：US4488255A

公开(公告)日：1984-12-11

申请号：US313916

申请日：1981-10-22

申请人： Dale L. Krisher ,  Sirus Chitsaz

发明人： Dale L. Krisher ,  Sirus Chitsaz

IPC分类号： G06F17/10 ,  G06F17/14 ,  G06F3/00 ,  G06F5/00

CPC分类号： G06F17/10 ,  G06F17/142

摘要： There is described a processing register particularly adapted for use in digital processing systems to implement various digital functions as high order digital filters and other structures which presently require complicated integrated circuit arrangements.The processing register operates in five modes which are a shift register mode with multiple fixed delays, a shift register with multiple fixed delays and a time slot interchanger, a shift register mode with an alternating word pair interchanger, a programmable delay shift register and as a discrete fourier transform preprocessing module.The processing register is particularly adaptable to operate with a high speed multiplier to implement various digital processing functions. In order to accommodate mode operation the processing register contains a main shift register and a computation register which are under the control of a control register which register accepts a control input word having bits thereof indicative of a particular mode of operation.The processing register further includes an independent storage register which shares overflow operation with the main storage register and which register can also be controlled by the control word during certain of the above described modes of operation. In order to provide flexibility the processing register contains a 1 to 2 multiplexer which is programmable according to the status of a second control word. The multiplexer register can operate in conjunction with the main and independent registers during certain other modes of operation. In order to accommodate the multiple modes of operation there is further included a sum and difference register whose inputs can be selected during mode operation to enable one to couple sum and difference digital signals to the multiplexer or to the inputs of the main and independent storage registers.In the configuration described data computation and control of the processing register is synchronized with the clock input and a word sync signal which signals define the relationship of all operations and thus enable one to perform complicated digital functions in a simple and reliable manner.

公开(公告)号：US4991173A

公开(公告)日：1991-02-05

申请号：US258993

申请日：1988-10-17

申请人： Dale L. Krisher

发明人： Dale L. Krisher

IPC分类号： H04J3/12

CPC分类号： H04J3/12

摘要： In pulse code modulation communications systems where network links, using A, AB and ABCD signaling systems having different sized bit patterns and signaling rates for signaling operations, are interfaced, apparatus is provided to control the mapping of signaling patterns at signaling rate conversion boundaries.

摘要翻译： 在脉冲编码调制通信系统中，使用具有不同大小的位模式的A，AB和ABCD信令系统以及用于信令操作的信令速率的网络链路进行接口，提供装置来控制信令速率转换边界处的信令模式的映射。

公开(公告)号：US5872780A

公开(公告)日：1999-02-16

申请号：US886724

申请日：1992-05-21

申请人： Sahabettin C. Demiray ,  Dale L. Krisher ,  William B. Weeber

发明人： Sahabettin C. Demiray ,  Dale L. Krisher ,  William B. Weeber

IPC分类号： H04J3/14 ,  H04J3/16 ,  H04Q11/04 ,  H04L12/52

CPC分类号： H04J3/14 ,  H04J3/1611 ,  H04J2203/006 ,  Y10S370/907

摘要： An internal signal within a SONET element has a transport format having overhead and payload mapped in a manner similar to the Synchronous Optical Network standard mapping, except having selected overhead bytes defined differently, including a byte used for communicating odd parity calculated over an odd number of bytes of a frame of the transport format to determine correct or incorrect parity, selected bytes used for inter-module automatic protection switching, and a pointer having a selected fixed value, along with an adjusted virtual tributary pointer in a virtual tributary mode.

摘要翻译： SONET元件内的内部信号具有以类似于同步光网络标准映射的方式映射的开销和有效载荷的传输格式，除了具有不同定义的所选开销字节之外，包括用于传送在奇数个 传输格式的帧的字节以确定正确或不正确的奇偶校验，用于模块间自动保护切换的所选字节，以及具有选定的固定值的指针以及虚拟辅助模式中调整的虚拟辅助指针。

公开(公告)号：US5185736A

公开(公告)日：1993-02-09

申请号：US351861

申请日：1989-05-12

申请人： Raymond E. Tyrrell ,  O. Lamar Bishop ,  William E. Powell ,  Dale L. Krisher ,  William H. Stephenson ,  M. Rodney Briscoe ,  Hal A. Thorne ,  Claude M. Hurlocker ,  V. Paul Runyon ,  Timothy J. Williams ,  Joseph E. Sutherland ,  William B. Weeber ,  Michael J. Gingell ,  Kenneth J. Stoia ,  William J. Fox ,  Jeffrey P. Jones ,  Richard M. Czerwiec ,  Ertugrul Baydar ,  Heinrich T. Sonnenberg ,  Richard Peters ,  Gus C. Sanders ,  Richard J. Sanders, Jr. ,  Francis G. Noser ,  Joseph L. Smith ,  Jak Yaemsiri ,  Camille A. Abu-Saba ,  Patrick M. Farrell ,  Wenkwei Rou ,  Victor W. Wilkerson ,  Mohammad S. Arani ,  Stephen C. Dunning ,  Keith Bernhardt ,  Dana Merrill ,  Michael Sutton

发明人： Raymond E. Tyrrell ,  O. Lamar Bishop ,  William E. Powell ,  Dale L. Krisher ,  William H. Stephenson ,  M. Rodney Briscoe ,  Hal A. Thorne ,  Claude M. Hurlocker ,  V. Paul Runyon ,  Timothy J. Williams ,  Joseph E. Sutherland ,  William B. Weeber ,  Michael J. Gingell ,  Kenneth J. Stoia ,  William J. Fox ,  Jeffrey P. Jones ,  Richard M. Czerwiec ,  Ertugrul Baydar ,  Heinrich T. Sonnenberg ,  Richard Peters ,  Gus C. Sanders ,  Richard J. Sanders, Jr. ,  Francis G. Noser ,  Joseph L. Smith ,  Jak Yaemsiri ,  Camille A. Abu-Saba ,  Patrick M. Farrell ,  Wenkwei Rou ,  Victor W. Wilkerson ,  Mohammad S. Arani ,  Stephen C. Dunning ,  Keith Bernhardt ,  Dana Merrill ,  Michael Sutton

IPC分类号： H04J3/08 ,  H04J3/16 ,  H04Q11/04

CPC分类号： H04J3/1611 ,  H04J3/08 ,  H04J2203/0048 ,  H04J2203/006

摘要： A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

公开(公告)号：US5740157A

公开(公告)日：1998-04-14

申请号：US887156

申请日：1992-05-21

申请人： Sahabettin C. Demiray ,  Dale L. Krisher ,  Raymond E. Tyrrell

发明人： Sahabettin C. Demiray ,  Dale L. Krisher ,  Raymond E. Tyrrell

IPC分类号： H04L29/14 ,  H04J3/14 ,  H04J3/16 ,  H04L12/24 ,  H04Q11/04 ,  H04L1/22

CPC分类号： H04J3/1611 ,  H04J3/14 ,  H04Q11/0407

摘要： Redundant facility payload signals (12, 14) received by redundant interface modules (16, 18) are redundantly provided (28, 30; 32, 34) to redundant downstream modules (24, 26) in an equipment (10). A non-symmetrical facility protection algorithm is resident in the B interface module (18). Symmetrical equipment protection algorithms are independently resident and operative in each module of pairs of identical A and B modules at each stage of the data stream. Module or data failures result in switchover only of the disabled data path or module so that the ability to transport payload is maintained and other modules or data paths are unaffected. Facility switchover is effected by detecting a working line failure and transmitting commands to switch the protection line to the A path modules. Equipment switchover is effected by checking for a working or protection module failure independently in each path and independently communicating independent switchover decisions to the other side and downstream. The methodology and mechanism are disclosed in a SONET element embodiment, although the invention is applicable in other contexts.

摘要翻译： 冗余接口模块（16,18）接收的冗余设施有效载荷信号（12,14）被冗余地提供给设备（10）中的冗余下游模块（24,26）（28,30; 32,34）。 非对称设备保护算法驻留在B接口模块（18）中。 在数据流的每个阶段，对称设备保护算法独立地驻留在每个相同A和B模块对中的模块中。 模块或数据故障导致只切换禁用的数据路径或模块，以便维护传输有效负载的能力，并且其他模块或数据路径不受影响。 通过检测工作线路故障并发送命令将保护线路切换到A路径模块来实现设备切换。 通过在每个路径中独立检查工作或保护模块故障并独立地将独立切换决策传递到另一侧和下游来实现设备切换。 在SONET元件实施例中公开了方法和机制，尽管本发明可应用于其它上下文。

公开(公告)号：US5633892A

公开(公告)日：1997-05-27

申请号：US279197

申请日：1994-07-22

申请人： Dale L. Krisher

发明人： Dale L. Krisher

IPC分类号： H04J3/16 ,  H04L25/49

CPC分类号： H04L25/4925 ,  H04J3/1623

摘要： Existing infrastructures such as DS1 or E1 are used at currently accepted rates to carry a third more information by using a hybrid encoding technique wherein a 4B3T encoding is done for the payload bits, while a 1B1T encoding technique is used for framing information. In this way, for example, a DS1 can be used at 1.54 Mbit per second to carry 2.058 Mbits of binary payload, while respecting the 8 kilobits of framing expected by DS1 hardware. Similarly, for example, an E1 infrastructure can be used at the accepted 2.048 Mbit per second rate to carry 2.560 Mbits of binary payload plus 128 kilobits of binary framing/CRC without having to change the accepted E1 framing techniques.

摘要翻译： 现有的基础设施如DS1或E1以目前被接受的速率使用，通过使用混合编码技术来携带第三更多的信息，其中对于有效载荷比特进行4B3T编码，而1B1T编码技术被用于构图信息。 以这种方式，例如，DS1可以以每秒1.54Mbit的速率使用，以承载2.058Mb的二进制有效载荷，同时遵循DS1硬件预期的8千比特的帧。 类似地，例如，可以以接受的2.048Mbit /秒速率使用E1基础设施来承载2.560Mb的二进制有效负载和128千比特的二进制帧/ CRC，而不必改变接受的E1成帧技术。

公开(公告)号：US5579323A

公开(公告)日：1996-11-26

申请号：US279215

申请日：1994-07-22

申请人： Dale L. Krisher

发明人： Dale L. Krisher

IPC分类号： H04J3/16 ,  H04Q11/04 ,  H04J3/00

CPC分类号： H04J3/1611 ,  H04J2203/0033 ,  H04J2203/0089 ,  Y10S370/907

摘要： A virtual tributary (VT) or tributary unit (TU) of a selected size is multiplexed with transport overhead and further multiplexed with framing bandwidth of an underlying transport technology for providing a virtual tributary/tributary unit plus transport link overhead plus transport framing for transport on a selected transport technology. This enables individual virtual tributaries/tributary units to be transported with defined line overhead and using existing transport technology framing. Several examples of underlying transport technologies used in conjunction with selected transport formats for VT-1.5 and VT-2 superframes are shown.

摘要翻译： 所选大小的虚拟支流（VT）或支路单元（TU）与传输开销多路复用，并进一步与底层传输技术的成帧带宽复用，以提供虚拟支路/支路单元加上传输链路开销加上用于传输的传输帧 选择运输技术。 这使得可以使用定义的线路开销和使用现有的传输技术框架来传输各个虚拟支路/支路单元。 显示了与VT-1.5和VT-2超帧的所选传输格式结合使用的底层传输技术的几个示例。

公开(公告)号：US5210762A

公开(公告)日：1993-05-11

申请号：US771038

申请日：1991-10-02

申请人： William B. Weeber ,  Dale L. Krisher

发明人： William B. Weeber ,  Dale L. Krisher

IPC分类号： H04J3/06 ,  H04Q11/04

CPC分类号： H04J3/0623 ,  H04J2203/006

摘要： A SONET pointer interpretation in system which an Alarm Indication Signal (AIS) of a first type is interpreted as a subset of Loss of Pointer (LOP) of a first type. Specific events are defined for entering an AIS type 1 state and for exiting this state. Specific events are also defined for entering an LOP type 1 state and for exiting this state. Finally, a truth table is defined for mapping these states into a valid pointer (NORM) state, an AIS of a second type state and an LOP of a second type state.