公开(公告)号：US6134623A

公开(公告)日：2000-10-17

申请号：US137670

申请日：1998-08-21

申请人： Raymond Eugene Garcia ,  John Richard Paveza

发明人： Raymond Eugene Garcia ,  John Richard Paveza

IPC分类号： G06F11/10 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4027 ,  G06F11/10

摘要： A system for coupling a host processor to a memory subsystem and enabling efficient transfer of data therebetween, where the memory subsystem responds to a data block read request by dispatching the designated data block and N data segments that are used by the receiver to determine the integrity of the data transfer. The system comprises a first bus system which couples the memory subsystem, via a bridge, to a controller that is, in turn, coupled by a second bus system to the host processor. The controller responds to a read request from the host processor for a first data block by dispatching to the bridge modified read requests that include (i) an address of the first data block and (ii) an address for the N data integrity segments. The bridge transfers the modified read requests to the memory subsystem, receives the first data block from the memory subsystem and transfers it to the controller. The bridge then receives the N data integrity segments, uses them to check the integrity of the data transfer, and discards them. Because of the aforesaid handling of the N data integrity segments, the bridge, upon receiving a next read request of data in addresses that are sequential to the first data block, determines there has been no discontinuity of sequential data block addresses.

摘要翻译： 一种用于将主机处理器耦合到存储器子系统并且能够在其之间有效传输数据的系统，其中存储器子系统通过调度指定的数据块和接收机使用的N个数据段来响应数据块读取请求以确定完整性 的数据传输。 该系统包括第一总线系统，其通过桥接将存储器子系统耦合到控制器，控制器又由第二总线系统耦合到主机处理器。 控制器通过调度到桥接修改的读取请求来响应来自主机处理器对于第一数据块的读取请求，该读取请求包括（i）第一数据块的地址和（ii）N个数据完整性段的地址。 桥将修改的读取请求传送到存储器子系统，从存储器子系统接收第一个数据块并将其传送到控制器。 然后，桥接器接收N个数据完整性段，使用它们来检查数据传输的完整性，并丢弃它们。 由于上述N个数据完整性段的处理，桥接器在接收到与第一数据块连续的地址中的数据的下一次读取请求时，确定顺序数据块地址没有不连续性。

公开(公告)号：US6065083A

公开(公告)日：2000-05-16

申请号：US138118

申请日：1998-08-21

申请人： Raymond Eugene Garcia ,  Steven Douglas Gerdt ,  John Richard Paveza

发明人： Raymond Eugene Garcia ,  Steven Douglas Gerdt ,  John Richard Paveza

IPC分类号： G06F13/12 ,  G06F13/00 ,  G06F13/16 ,  G06P13/00

CPC分类号： G06F13/16

摘要： A computing system that incorporates the invention includes a host processor which is coupled to a memory subsystem via a first bus system, a controller device and a second bus system. The controller device includes memory for storing plural Scripts for replay to the host processor, for instance, via the second bus system. A Script is an instruction set used to execute operations on a controller device. Each Script includes one or more addresses where either message or status data (or other operational data) can be found which is to be inserted, prior to dispatch of the Script. During operation of the computing system, the memory subsystem is caused, as a result of its operation, to issue an instruction to the controller device to dispatch a Script to, for instance, the host processor. The controller device responds by accessing the required Script, playing the Script which results in accesses to locally stored operational data for inclusion into the Script. Local storage of this data avoids unnecessary data transfers over the bus system to the memory subsystem to obtain the required data for inclusion into a Script.

摘要翻译： 结合本发明的计算系统包括经由第一总线系统，控制器设备和第二总线系统耦合到存储器子系统的主机处理器。 控制器设备包括用于例如经由第二总线系统将用于重播的多个脚本存储到主机处理器的存储器。 脚本是用于在控制器设备上执行操作的指令集。 每个脚本包括一个或多个地址，在发出脚本之前，可以找到要插入的消息或状态数据（或其他操作数据）。 在计算系统的操作期间，作为其操作的结果，引起存储器子系统向控制器设备发出指令以将脚本发送到例如主机处理器。 控制器设备通过访问所需的脚本进行响应，播放脚本，导致访问本地存储的操作数据以包含在脚本中。 该数据的本地存储避免了通过总线系统到存储器子系统的不必要的数据传输，以获得包含在脚本中的所需数据。