Patent search ap:("Raytheon Company") AND inv:"Christos Thomidis" Page 1

1.

发明授权
Semiconductor structure having both enhancement mode group III-N high electron mobility transistors and depletion mode group III-N high electron mobility transistors 有权

公开(公告)号：US11594627B2

公开(公告)日：2023-02-28

申请号：US17380379

申请日：2021-07-20

Applicant: Raytheon Company

Inventor： Kiuchul Hwang , Brian D. Schultz , John Logan , Christos Thomidis

IPC: H01L29/778 , H01L21/223 , H01L29/20 , H01L29/207 , H01L29/66

Abstract: An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.

2.

发明申请
SEMICONDUCTOR STRUCTURE HAVING BOTH ENHANCEMENT MODE GROUP III-N HIGH ELECTRON MOBILITY TRANSISTORS AND DEPLETION MODE GROUP III-N HIGH ELECTRON MOBILITY TRANSISTORS 有权

公开(公告)号：US20210351288A1

公开(公告)日：2021-11-11

申请号：US17380379

申请日：2021-07-20

Applicant: Raytheon Company

Inventor： Kiuchul Hwang , Brian D. Schultz , John Logan , Christos Thomidis

IPC: H01L29/778 , H01L21/223 , H01L29/20 , H01L29/207 , H01L29/66

Abstract: An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.

3.

发明授权
Semiconductor structure having both enhancement mode group III-N high electron mobility transistors and depletion mode group III-N high electron mobility transistors 有权

公开(公告)号：US11101378B2

公开(公告)日：2021-08-24

申请号：US16379077

申请日：2019-04-09

Applicant: Raytheon Company

Inventor： Kiuchul Hwang , Brian D. Schultz , John Logan , Christos Thomidis

IPC: H01L29/778 , H01L21/223 , H01L29/20 , H01L29/207 , H01L29/66

Abstract: An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.

4.

发明申请
SEMICONDUCTOR STRUCTURE HAVING BOTH ENHANCEMENT MODE GROUP III-N HIGH ELECTRON MOBILITY TRANSISTORS AND DEPLETION MODE GROUP III-N HIGH ELECTRON MOBILITY TRANSISTORS 审中-公开

公开(公告)号：US20200328296A1

公开(公告)日：2020-10-15

申请号：US16379077

申请日：2019-04-09

Applicant: Raytheon Company

Inventor： Kiuchul Hwang , Brian D. Schultz , John Logan , Christos Thomidis

IPC: H01L29/778 , H01L29/20 , H01L29/207 , H01L29/66 , H01L21/223

Abstract: An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.

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