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    METHOD FOR DETERMINING INTERFACE TIMING OF INTEGRATED CIRCUIT AUTOMATICALLY AND RELATED MACHINE READABLE MEDIUM THEREOF
    1.
    发明申请
    METHOD FOR DETERMINING INTERFACE TIMING OF INTEGRATED CIRCUIT AUTOMATICALLY AND RELATED MACHINE READABLE MEDIUM THEREOF 有权
    自动确定集成电路接口时序的方法及相关机器可读介质

    公开(公告)号：US20140223398A1

    公开(公告)日：2014-08-07

    申请号：US14051455

    申请日：2013-10-11

    Applicant: Realtek Semiconductor Corp.

    Inventor： Mei-Li Yu ,  Ting-Hsiung Wang ,  Yu-Lan Lo ,  Shu-Yi Kao

    IPC: G06F17/50

    CPC classification number: G06F1/10 ,  G06F17/5031

    Abstract: A method for determining an interface timing of an integrated circuit includes: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface port of the netlist file according to the netlist file and the timing constraint file; determining a first transmission path and a load on the first transmission path between the first interface port and a specific circuit element in the netlist file; generating an interface circuit file according to the first transmission path and the load on the first transmission path; and calculating a first signal transmission time of the first transmission path out according to the interface circuit file.

    Abstract translation: 一种用于确定集成电路的接口定时的方法包括：读取集成电路的网表文件和定时约束文件，并根据网表文件和定时约束文件确定网表文件的第一接口端口; 确定网表列表文件中的第一接口端口和特定电路元件之间的第一传输路径上的第一传输路径和负载; 根据第一传输路径和第一传输路径上的负载生成接口电路文件; 以及根据所述接口电路文件计算出所述第一传输路径的第一信号传输时间。

    Simulation method for mixed-signal circuit system and related electronic device
    2.
    发明授权
    Simulation method for mixed-signal circuit system and related electronic device 有权

    公开(公告)号：US10521529B2

    公开(公告)日：2019-12-31

    申请号：US15628636

    申请日：2017-06-20

    Applicant: Realtek Semiconductor Corp.

    Inventor： Ying-Chieh Chen ,  Mei-Li Yu ,  Ting-Hsiung Wang ,  Yu-Lan Lo ,  Shu-Yi Kao

    IPC: G06F17/50 ,  G01R31/3167

    Abstract: A simulation method for a mixed-signal circuit system includes: detecting a plurality of registers and a clock signal included in the mixed-signal circuit system; performing a timing analysis converting operation upon a circuit block coupled between any two register of the plurality of registers to obtain a converted circuit system; and performing a Static Timing Analysis operation upon the converted circuit system; wherein when the circuit block is convertible into a combinational circuit block, the timing analysis converting operation includes: converting the circuit block to the combinational circuit block, wherein the combinational circuit block is logic gate-level.

    ESTIMATION METHOD USED IN INTEGRATED CIRCUIT CHIP OF INTEGRATED CIRCUIT DESIGN AND INTEGRATED CIRCUIT CHIP
    3.
    发明申请
    ESTIMATION METHOD USED IN INTEGRATED CIRCUIT CHIP OF INTEGRATED CIRCUIT DESIGN AND INTEGRATED CIRCUIT CHIP 有权

    公开(公告)号：US20250013814A1

    公开(公告)日：2025-01-09

    申请号：US18668230

    申请日：2024-05-19

    Applicant: Realtek Semiconductor Corp.

    Inventor： Wei-Ming Huang ,  Mei-Li Yu ,  Yu-Lan Lo

    IPC: G06F30/392

    Abstract: A method of an integrated circuit chip, includes: calculating a first slope of distance-to-spatial relation under first design condition according to spatial distance difference between two circuit elements within integrated circuit chip and a spatial process variation under first design condition; calculating a second slope of the distance-to-spatial relation under a second design condition according to the spatial distance difference and a spatial process variation under second design condition; calculating a ratio coefficient and an exponential coefficient according to the first slope, the second slope, a global process variation under the first design condition, and a global process variation under the second design condition; calculating a third slope of the distance-to-spatial relation under a third design condition according to the ratio coefficient and the exponential coefficient; and estimating a spatial process variation under the third design condition according to the third slope and the spatial distance difference.

    METHOD FOR ESTABLISHING VARIATION MODEL RELATED TO CIRCUIT CHARACTERISTICS FOR PERFORMING CIRCUIT SIMULATION, AND ASSOCIATED CIRCUIT SIMULATION SYSTEM
    4.
    发明公开
    METHOD FOR ESTABLISHING VARIATION MODEL RELATED TO CIRCUIT CHARACTERISTICS FOR PERFORMING CIRCUIT SIMULATION, AND ASSOCIATED CIRCUIT SIMULATION SYSTEM 审中-公开

    公开(公告)号：US20230142132A1

    公开(公告)日：2023-05-11

    申请号：US17693396

    申请日：2022-03-13

    Applicant: Realtek Semiconductor Corp.

    Inventor： Wei-Ming Huang ,  Szu-Ying Huang ,  Mei-Li Yu ,  Yu-Lan Lo

    IPC: G06F30/3308 ,  G06N7/08

    CPC classification number: G06F30/3308 ,  G06N7/08 ,  G06F2119/02

    Abstract: A method for establishing a variation model related to circuit characteristics for performing circuit simulation includes: performing first, second, third, and fourth Monte Carlo simulation operations according to a first netlist file and predetermined process model data to generate a first, a second, a third, and a fourth performance simulation results, respectively, where the first netlist file is arranged to indicate a basic circuit in a circuit system; and execute a performance simulation results expansion procedure according to the first, the second, the third, and the fourth performance simulation results to generate a plurality of performance simulation results to establish the variation model, for performing the circuit simulation to generate at least one circuit simulation result according to one or more performance simulation results among the plurality of performance simulation results, where the number of the plurality of performance simulation results is greater than four.

    METHOD AND APPARATUS FOR ADAPTIVE VOLTAGE SCALING TO ELIMINATE DELAY VARIATION OF WHOLE DESIGN
    5.
    发明申请
    METHOD AND APPARATUS FOR ADAPTIVE VOLTAGE SCALING TO ELIMINATE DELAY VARIATION OF WHOLE DESIGN 审中-公开

    公开(公告)号：US20190384868A1

    公开(公告)日：2019-12-19

    申请号：US16355837

    申请日：2019-03-17

    Applicant: Realtek Semiconductor Corp.

    Inventor： Mei-Li Yu ,  Ying-Chieh Chen ,  Yu-Lan Lo ,  Hsin-Chang Lin ,  Shu-Yi Kao

    IPC: G06F17/50

    Abstract: A method and apparatus for adaptive voltage scaling to eliminate delay variation of a whole design are provided. The method may include: reading a circuit simulation netlist file, a circuit design database, and a path list; building a delay variation database of each minimum unit within multiple minimum units of the whole design under various voltage levels according to the circuit design database; utilizing an initial voltage level to be a voltage level of a driving voltage of the whole design to apply the initial voltage level to the whole design, and performing static timing analysis (STA) on the whole design, to determine whether any timing violation path exists in the path list; and selectively adjusting the voltage level of the driving voltage and re-performing the STA until no timing violation path exists.

    TIMING ANALYSIS METHOD FOR NON-STANDARD CELL CIRCUIT AND ASSOCIATED MACHINE READABLE MEDIUM
    6.
    发明申请
    TIMING ANALYSIS METHOD FOR NON-STANDARD CELL CIRCUIT AND ASSOCIATED MACHINE READABLE MEDIUM 审中-公开
    非标准电路电路及相关机器可读介质的时序分析方法

    公开(公告)号：US20150067623A1

    公开(公告)日：2015-03-05

    申请号：US14450279

    申请日：2014-08-03

    Applicant: REALTEK SEMICONDUCTOR CORP.

    Inventor： Ying-Chieh Chen ,  Mei-Li Yu ,  Ting-Hsiung Wang ,  Yu-Lan Lo ,  Shu-Yi Kao

    IPC: G06F17/50

    CPC classification number: G06F17/5031 ,  G06F2217/84

    Abstract: A timing analysis method applied for a non-standard cell circuit, includes: identifying at least a first register and a second register from the circuit; calculating at least one path delay of at least one path between the first register and the second register; calculating a first register clock delay from a first clock source to a first register clock input terminal of the first register; calculating a second register clock delay from a second clock source to a second register clock input terminal of the second register; and determining whether timing violation takes place in respect of the second register according to the path delay, the first register clock delay, the second register clock delay, and a first register delay of the first register.

    Abstract translation: 一种应用于非标准单元电路的定时分析方法，包括：从电路识别至少第一寄存器和第二寄存器; 计算所述第一寄存器和所述第二寄存器之间的至少一个路径的至少一个路径延迟; 计算从第一时钟源到第一寄存器的第一寄存器时钟输入端的第一寄存器时钟延迟; 计算从第二时钟源到第二寄存器的第二寄存器时钟输入端的第二寄存器时钟延迟; 以及根据所述路径延迟，所述第一寄存器时钟延迟，所述第二寄存器时钟延迟以及所述第一寄存器的第一寄存器延迟确定是否针对所述第二寄存器发生定时违反。

    METHOD FOR CHECKING I/O CELL CONNECTIONS AND ASSOCIATED COMPUTER READABLE MEDIUM
    7.
    发明申请
    METHOD FOR CHECKING I/O CELL CONNECTIONS AND ASSOCIATED COMPUTER READABLE MEDIUM 审中-公开
    检查I / O单元连接和相关计算机可读介质的方法

    公开(公告)号：US20130298095A1

    公开(公告)日：2013-11-07

    申请号：US13875263

    申请日：2013-05-01

    Applicant: REALTEK SEMICONDUCTOR CORP.

    Inventor： Mei-Li Yu ,  Yu-Lan Lo ,  Shu-Yi Kao

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: A computer readable medium includes a program code for checking whether an I/O cell of a chip design has a connection error or not, where the chip design includes a plurality of I/O cells and a plurality of blocks, and when the program code is executed by a processor, the program code executes following steps: checking a connection between the I/O cell and a block by utilizing a check item corresponding to an attribute of the I/O cell to generate a checking result; and determining whether the I/O cell has a connection error according to the checking result.

    Abstract translation: 计算机可读介质包括用于检查芯片设计的I / O单元是否具有连接错误的程序代码，其中芯片设计包括多个I / O单元和多个块，并且当程序代码 由处理器执行，程序代码执行以下步骤：通过利用与I / O单元的属性相对应的检查项来检查I / O单元和块之间的连接以产生检查结果; 以及根据检查结果确定I / O单元是否具有连接错误。

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