公开(公告)号：US09224447B2

公开(公告)日：2015-12-29

申请号：US14259568

申请日：2014-04-23

Applicant: Regents of the University of Minnesota

Inventor： Jian-Ping Wang ,  Jonathan D. Harms

IPC: G11C11/16 ,  G11C5/08

CPC classification number: G11C11/16 ,  G11C5/08 ,  G11C11/1659

Abstract: A cell array includes a logic connection line, a plurality of bit selection lines, and a plurality of cells. Each cell includes a memory element connected to a respective bit selection line and a logic switching element that selectively connects the memory element to the logic connection line. When logic switching elements of multiple separate cells connect their respective memory elements to the logic connection line, the memory elements connected to the logic connection line operate as a logic device with an output of the logic device stored in one of the memory elements.

Abstract translation: 单元阵列包括逻辑连接线，多个位选择线和多个单元。 每个单元包括连接到相应位选择线的存储元件和选择性地将存储元件连接到逻辑连接线的逻辑开关元件。 当多个单独单元的逻辑开关元件将其各自的存储器元件连接到逻辑连接线时，连接到逻辑连接线的存储元件作为逻辑器件工作，逻辑器件的输出存储在存储器元件之一中。