Abstract:
An eFuse with at least one fuse unit is provided. The fuse unit includes a common node, a sensing unit with a first input terminal and a second input terminal, at least one fuse coupled between the common node and the first input terminal of the sensing unit with a resistance, and a switching unit coupled between the common node and the second input terminal of the sensing unit. A resistance of the switching unit is equivalent to a first resistance in a normal mode and equivalent to a second resistance in a test mode, and the second resistance is higher than the first resistance. The sensing unit generates an output signal indicating whether the fuse is blown or not according to the resistances of the fuse and the switching unit.
Abstract:
An eFuse with at least one fuse unit is provided. The fuse unit includes a common node, a sensing unit with a first input terminal and a second input terminal, at least one fuse coupled between the common node and the first input terminal of the sensing unit with a resistance, and a switching unit coupled between the common node and the second input terminal of the sensing unit. A resistance of the switching unit is equivalent to a first resistance in a normal mode and equivalent to a second resistance in a test mode, and the second resistance is higher than the first resistance. The sensing unit generates an output signal indicating whether the fuse is blown or not according to the resistances of the fuse and the switching unit.
Abstract:
An eFuse with at least one fuse unit is provided. The fuse unit includes a first common node providing a first reference voltage, a second common node providing a second reference voltage, at least one fuse coupled to the first common node, and a determining unit coupled between the fuse and the second common node, generating an output signal indicating whether the fuse is blown or not according to a first condition in a normal mode and a second condition in a test mode.
Abstract:
An electrically programmable fuse (e-fuse) apparatus includes an e-fuse macro and a switch device. The e-fuse macro is disposed in an integrated circuit, and has a plurality of e-fuse units. The switch device is disposed in the integrated circuit, and has an output node coupled to the e-fuse units and a first input node coupled to a first power source which supplies a first reference voltage acting as a programming voltage of the e-fuse macro. The switch device connects the first power source to the e-fuse units when the e-fuse macro is operated under a programming mode.
Abstract:
An exemplary embodiment of an efuse device is provided, operating in a write mode and a read mode and comprising a source line, a cell, a blow device, and a sensing circuit. The cell has a first terminal coupled to the source line and a second terminal. The blow device is coupled between the second terminal of the cell and a ground terminal. The blow device is turned on in the read mode. The sensing circuit is coupled to the first terminal of the cell and the ground terminal, and is arranged to determine a state of the cell.
Abstract:
The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.
Abstract:
Disclosed is a build-in self-diagnosis and repair method and apparatus in a memory with syndrome identification. It applies a fail-pattern identification and a syndrome-format structure to identify at least one type of faulty syndrome in the memory during a memory testing, then generates and exports fault syndrome information associated with the corresponding faulty syndrome. According to the fault syndrome information, the method applies a redundancy analysis algorithm, allocates spare memory elements and repairs the faulty cells in the memory. The syndrome-format structure respectively applies single-faulty-word-syndrome format, faulty-row-segment-syndrome format, and faulty-column-segment-syndrome format for different faulty syndromes, such as faulty row segments and single faulty words, faulty column segments and single faulty words, all of single faulty words, faulty row segments and faulty column segments, and so on.
Abstract:
The disclosure relates to a voltage converter, converting a first signal of a first voltage to output a second signal of a second voltage. A level shifter receives the first signal to generate the second signal. An isolation circuit is coupled to the output of the level shifter, passing the second signal out. When the input of voltage converter is floated, the isolation circuit stops passing the second signal as the output, instead, the isolation circuit outputs a substitution signal having a predetermined voltage level irrelevant to the input of the level shifter.
Abstract:
The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.
Abstract:
The disclosure relates to a voltage converter, converting a first signal of a first voltage to output a second signal of a second voltage. A level shifter receives the first signal to generate the second signal. An isolation circuit is coupled to the output of the level shifter, passing the second signal out. When the input of voltage converter is floated, the isolation circuit stops passing the second signal as the output, instead, the isolation circuit outputs a substitution signal having a predetermined voltage level irrelevant to the input of the level shifter.