公开(公告)号：US09170637B2

公开(公告)日：2015-10-27

申请号：US14685349

申请日：2015-04-13

Applicant: Renesas Electronics Corporation

Inventor： Mamoru Sakugawa ,  Masamichi Fujito ,  Jun Setogawa ,  Masaru Takahashi ,  Shinsuke Yoshimura

IPC: G06F1/32 ,  G06F1/08

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A data processing device, includes a central processing unit configured to operate in accordance with a program; a register capable of setting a first mode and a second mode; a non-volatile memory; a sequencer configured to control the non-volatile memory; and a first clock circuit for supplying a first clock to the central processing unit and the non-volatile memory, wherein the first mode is a mode in which the central processing unit is operated within a first range of an external supply voltage, wherein the second mode is a mode in which the central processing unit is operated within a second range of the external supply voltage, the second range includes the first range and a relatively low voltage lower than the lower limit voltage of the first range.

Abstract translation: 一种数据处理装置，包括：中央处理单元，被配置为根据程序进行操作; 能够设置第一模式和第二模式的寄存器; 非易失性存储器; 配置成控制所述非易失性存储器的定序器; 以及第一时钟电路，用于向中央处理单元和非易失性存储器提供第一时钟，其中第一模式是中央处理单元在外部电源电压的第一范围内操作的模式，其中第二时钟 模式是中央处理单元在外部电源电压的第二范围内操作的模式，第二范围包括低于第一范围的下限电压的第一范围和相对低的电压。